feat: top module changes

ElectronicCats · Jan 12, 2025 · 695ff7d · 695ff7d
1 parent f0c1da4
commit 695ff7d
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Showing 2 changed files with 0 additions and 15 deletions.
diff --git a/src/tt_um_waves.v b/src/tt_um_waves.v
@@ -1,6 +1,4 @@
 module tt_um_waves (
-    input wire VPWR,
-    input wire VGND,
     input  wire [7:0] ui_in,    // ui_in[0] for UART RX
     output reg [7:0] uo_out,    // Dedicated outputs: uo_out[2:0] = {WS, SD, SCK} for I2S
     input  wire [7:0] uio_in,   // GPIO for encoder inputs

diff --git a/test/tb.v b/test/tb.v
@@ -1,6 +1,3 @@
-`default_nettype none
-`timescale 1ns / 1ps
-
 module tb ();
 
   initial begin
@@ -19,18 +16,8 @@ module tb ();
   wire [7:0] uio_out;
   wire [7:0] uio_oe;
 
-  // Declare VPWR and VGND for gate-level testing
-`ifdef GL_TEST
-  wire VPWR = 1'b1;  
-  wire VGND = 1'b0;  
-`endif
-
   // Replace tt_um_example with your module name:
   tt_um_waves user_project (
-`ifdef GL_TEST
-      .VPWR(VPWR),
-      .VGND(VGND),
-`endif
       .ui_in  (ui_in),
       .uo_out (uo_out),
       .uio_in (uio_in),