feat: files update

src/tt_um_waves.v

@@ -1,4 +1,6 @@
 module tt_um_waves (
+    input wire VPWR,
+    input wire VGND,
     input  wire [7:0] ui_in,    // ui_in[0] for UART RX
     output reg [7:0] uo_out,    // Dedicated outputs: uo_out[2:0] = {WS, SD, SCK} for I2S
     input  wire [7:0] uio_in,   // GPIO for encoder inputs

test/Makefile

@@ -5,14 +5,13 @@
 SIM ?= icarus
 TOPLEVEL_LANG ?= verilog
 SRC_DIR = $(PWD)/../src
-PROJECT_SOURCES = tt_um_waves.v
+PROJECT_SOURCES = project.v
 
 ifneq ($(GATES),yes)
 
 # RTL simulation:
 SIM_BUILD				= sim_build/rtl
 VERILOG_SOURCES += $(addprefix $(SRC_DIR)/,$(PROJECT_SOURCES))
-COMPILE_ARGS 		+= -I$(SRC_DIR)
 
 else
 
@@ -31,6 +30,9 @@ VERILOG_SOURCES += $(PWD)/gate_level_netlist.v
 
 endif
 
+# Allow sharing configuration between design and testbench via `include`:
+COMPILE_ARGS 		+= -I$(SRC_DIR)
+
 # Include the testbench sources:
 VERILOG_SOURCES += $(PWD)/tb.v
 TOPLEVEL = tb
@@ -39,4 +41,4 @@ TOPLEVEL = tb
 MODULE = test
 
 # include cocotb's make rules to take care of the simulator setup
-include $(shell cocotb-config --makefiles)/Makefile.sim
+include $(shell cocotb-config --makefiles)/Makefile.sim

test/tb.gtkw

@@ -1,3 +1,4 @@
+
 [*]
 [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
 [*] Mon Nov 20 16:00:28 2023

test/tb.v

@@ -1,12 +1,8 @@
 `default_nettype none
 `timescale 1ns / 1ps
 
-/* This testbench just instantiates the module and makes some convenient wires
-   that can be driven / tested by the cocotb test.py.
-*/
 module tb ();
 
-  // Dump the signals to a VCD file. You can view it with gtkwave or surfer.
   initial begin
     $dumpfile("tb.vcd");
     $dumpvars(0, tb);
@@ -25,8 +21,8 @@ module tb ();
 
   // Declare VPWR and VGND for gate-level testing
 `ifdef GL_TEST
-  reg VPWR;  // Drive power
-  reg VGND;  // Drive ground
+  wire VPWR = 1'b1;  
+  wire VGND = 1'b0;  
 `endif
 
   // Replace tt_um_example with your module name:
@@ -46,28 +42,18 @@ module tb ();
   );
 
   // Clock generation
-  always #5 clk = ~clk;  // 10-unit clock period
+  always #5 clk = ~clk;
 
-  // Testbench initialization
   initial begin
-    // Initialize signals
     clk = 0;
     rst_n = 0;
     ena = 0;
     ui_in = 8'b0;
     uio_in = 8'b0;
 
-`ifdef GL_TEST
-    // Initialize power and ground for gate-level testing
-    VPWR = 1'b1;
-    VGND = 1'b0;
-`endif
-
-    // Apply reset
     #10 rst_n = 1;
     ena = 1;
 
-    // Simulation duration
     #1000 $finish;
   end