A fully parameterized and generic Verilog implementation of the suggested modular SRAM-based indirectly-indexed hierarchical-search TCAM (IITCAM), together with other approaches are provided as open source hardware. A run-in-batch flow manager to simulate and synthesize different designs with various parameters in batch using Altera's ModelSim and Quartus is also provided.
LICENSE: BSD 3-Clause ("BSD New" or "BSD Simplified") license.
Please refer to the full paper for more information: A. M.S. Abdelhadi, G. G.F. Lemieux, and L. Shannon, "Modular Block-RAM-Based Longest-Prefix Match Ternary Content-Addressable Memories," in Proceedings of the 2018 International Conference on Field-Programmable Logic and Applications (FPL '18), August 2018.