Lane Detection on FPGA-HW/SW part with SDSoC

Realization of Advance Lane Detection Algorithm on Xilinx ZYNQ-7000 using SDSoC platform.

This project realized in C++ using with OpenCV and xfOpenCV Libraries.
It is a sub-task of "REALIZATION OF LANE DETECTION ALGORITHMS ON FPGA USING SDSOC AND VIVADO" graduate project at Istanbul Technical University, June 2018.

Please visit main repository for more details:

Project Repositories

1-) Main Repo -Full Project-: Lane Detection with implementation on FPGA
2-) C++ with OpenCV on just CPU without any acceleration with FPGA: Lane Detection on CPU Pure Software
3.1-) ✔️✔️ (This Repository) C++ with OpenCV on Arm processor and xfopencv on Hardware in Zynq-7000 series FPGA's, all steps of algorithms Lane Detection on FPGA-HW/SW part with SDSoC
3.2-) Verilog on hardware, only preprocess step: Lane Detection on FPGA-HW part with VIVADO

TODO

• Add project settings files
  

Lane Detection on FPGA-SW part with SDSoC

Dependencies

• Xilinx SDx Development Environments (tested version 2018.1 )
  
• OpenCV 2.4 (tested at windows platform (builded for windows) )
  
• OpenCV 2.4 for ARM processor (tested on Zedboard (builded for ARCH32 architecture))
  
• Xilinx xfOpenCV Library
  

Contributors

This project is a part of graduate project which is named as "REALIZATION OF LANE DETECTION ALGORITHMS ON FPGA USING SDSOC AND VIVADO" at Istanbul Technical University, June 2018.

Project members:
Yakup GÖRÜR ([email protected], [email protected]) - Software and SDSoC Platform
Mehmet Akif AKKAYA ([email protected]) - VIVADO Platform
Assoc. Prof. Dr. Sıddıka Berna ÖRS YALÇIN (Advisor)

** This project was supported by the Scientific and Technological Research Council of Turkey (TUBITAK).