missing initialization of mtvec register

virtualsquare · Nov 17, 2024 · 5733f1d · 5733f1d
1 parent ceae987
commit 5733f1d
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/src/uriscv/processor.cc b/src/uriscv/processor.cc
@@ -273,6 +273,7 @@ void Processor::Reset(Word pc, Word sp) {
   csrWrite(TIME, 0);
   csrWrite(PRID, id);
   csrWrite(MIP, 0);
+  csrWrite(MTVEC, 0);
   mode = 0x3;
 
   currPC = pc;