fpga/common: Add queue to scheduler feedback

Signed-off-by: Alex Forencich <[email protected]>
ucsdsysnet · Mar 3, 2024 · 737a6cc · 737a6cc
1 parent 2ec1c55
commit 737a6cc
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Showing 8 changed files with 89 additions and 14 deletions.
diff --git a/fpga/common/rtl/mqnic_interface.v b/fpga/common/rtl/mqnic_interface.v
@@ -2227,15 +2227,18 @@ wire [SCHEDULERS-1:0]                       tx_sched_req_ready;
 
 wire [SCHEDULERS-1:0]                       tx_sched_status_dequeue_empty;
 wire [SCHEDULERS-1:0]                       tx_sched_status_dequeue_error;
+wire [SCHEDULERS*TX_QUEUE_INDEX_WIDTH-1:0]  tx_sched_status_dequeue_queue;
 wire [SCHEDULERS*REQ_TAG_WIDTH-1:0]         tx_sched_status_dequeue_tag;
 wire [SCHEDULERS-1:0]                       tx_sched_status_dequeue_valid;
 
 wire [SCHEDULERS-1:0]                       tx_sched_status_start_error;
 wire [SCHEDULERS*DMA_CLIENT_LEN_WIDTH-1:0]  tx_sched_status_start_len;
+wire [SCHEDULERS*TX_QUEUE_INDEX_WIDTH-1:0]  tx_sched_status_start_queue;
 wire [SCHEDULERS*REQ_TAG_WIDTH-1:0]         tx_sched_status_start_tag;
 wire [SCHEDULERS-1:0]                       tx_sched_status_start_valid;
 
 wire [SCHEDULERS*DMA_CLIENT_LEN_WIDTH-1:0]  tx_sched_status_finish_len;
+wire [SCHEDULERS*TX_QUEUE_INDEX_WIDTH-1:0]  tx_sched_status_finish_queue;
 wire [SCHEDULERS*REQ_TAG_WIDTH-1:0]         tx_sched_status_finish_tag;
 wire [SCHEDULERS-1:0]                       tx_sched_status_finish_valid;
 
@@ -2247,15 +2250,18 @@ wire                             tx_req_ready;
 
 wire                             tx_status_dequeue_empty;
 wire                             tx_status_dequeue_error;
+wire [TX_QUEUE_INDEX_WIDTH-1:0]  tx_status_dequeue_queue;
 wire [REQ_TAG_WIDTH-1:0]         tx_status_dequeue_tag;
 wire                             tx_status_dequeue_valid;
 
 wire                             tx_status_start_error;
 wire [DMA_CLIENT_LEN_WIDTH-1:0]  tx_status_start_len;
+wire [TX_QUEUE_INDEX_WIDTH-1:0]  tx_status_start_queue;
 wire [REQ_TAG_WIDTH-1:0]         tx_status_start_tag;
 wire                             tx_status_start_valid;
 
 wire [DMA_CLIENT_LEN_WIDTH-1:0]  tx_status_finish_len;
+wire [TX_QUEUE_INDEX_WIDTH-1:0]  tx_status_finish_queue;
 wire [REQ_TAG_WIDTH-1:0]         tx_status_finish_tag;
 wire                             tx_status_finish_valid;
 
@@ -2366,15 +2372,18 @@ for (n = 0; n < SCHEDULERS; n = n + 1) begin : sched
          */
         .s_axis_tx_status_dequeue_empty(tx_sched_status_dequeue_empty[n +: 1]),
         .s_axis_tx_status_dequeue_error(tx_sched_status_dequeue_error[n +: 1]),
+        .s_axis_tx_status_dequeue_queue(tx_sched_status_dequeue_queue[n*TX_QUEUE_INDEX_WIDTH +: TX_QUEUE_INDEX_WIDTH]),
         .s_axis_tx_status_dequeue_tag(tx_sched_status_dequeue_tag[n*REQ_TAG_WIDTH_INT +: REQ_TAG_WIDTH_INT]),
         .s_axis_tx_status_dequeue_valid(tx_sched_status_dequeue_valid[n +: 1]),
 
         .s_axis_tx_status_start_error(tx_sched_status_start_error[n +: 1]),
         .s_axis_tx_status_start_len(tx_sched_status_start_len[n*DMA_CLIENT_LEN_WIDTH +: DMA_CLIENT_LEN_WIDTH]),
+        .s_axis_tx_status_start_queue(tx_sched_status_start_queue[n*TX_QUEUE_INDEX_WIDTH +: TX_QUEUE_INDEX_WIDTH]),
         .s_axis_tx_status_start_tag(tx_sched_status_start_tag[n*REQ_TAG_WIDTH_INT +: REQ_TAG_WIDTH_INT]),
         .s_axis_tx_status_start_valid(tx_sched_status_start_valid[n +: 1]),
 
         .s_axis_tx_status_finish_len(tx_sched_status_finish_len[n*DMA_CLIENT_LEN_WIDTH +: DMA_CLIENT_LEN_WIDTH]),
+        .s_axis_tx_status_finish_queue(tx_sched_status_finish_queue[n*TX_QUEUE_INDEX_WIDTH +: TX_QUEUE_INDEX_WIDTH]),
         .s_axis_tx_status_finish_tag(tx_sched_status_finish_tag[n*REQ_TAG_WIDTH_INT +: REQ_TAG_WIDTH_INT]),
         .s_axis_tx_status_finish_valid(tx_sched_status_finish_valid[n +: 1]),
 
@@ -2442,15 +2451,18 @@ if (SCHEDULERS > 1) begin
          */
         .s_axis_status_dequeue_empty(tx_status_dequeue_empty),
         .s_axis_status_dequeue_error(tx_status_dequeue_error),
+        .s_axis_status_dequeue_queue(tx_status_dequeue_queue),
         .s_axis_status_dequeue_tag(tx_status_dequeue_tag),
         .s_axis_status_dequeue_valid(tx_status_dequeue_valid),
 
         .s_axis_status_start_error(tx_status_start_error),
         .s_axis_status_start_len(tx_status_start_len),
+        .s_axis_status_start_queue(tx_status_start_queue),
         .s_axis_status_start_tag(tx_status_start_tag),
         .s_axis_status_start_valid(tx_status_start_valid),
 
         .s_axis_status_finish_len(tx_status_finish_len),
+        .s_axis_status_finish_queue(tx_status_finish_queue),
         .s_axis_status_finish_tag(tx_status_finish_tag),
         .s_axis_status_finish_valid(tx_status_finish_valid),
 
@@ -2468,15 +2480,18 @@ if (SCHEDULERS > 1) begin
          */
         .m_axis_status_dequeue_empty(tx_sched_status_dequeue_empty),
         .m_axis_status_dequeue_error(tx_sched_status_dequeue_error),
+        .m_axis_status_dequeue_queue(tx_sched_status_dequeue_queue),
         .m_axis_status_dequeue_tag(tx_sched_status_dequeue_tag),
         .m_axis_status_dequeue_valid(tx_sched_status_dequeue_valid),
 
         .m_axis_status_start_error(tx_sched_status_start_error),
         .m_axis_status_start_len(tx_sched_status_start_len),
+        .m_axis_status_start_queue(tx_sched_status_start_queue),
         .m_axis_status_start_tag(tx_sched_status_start_tag),
         .m_axis_status_start_valid(tx_sched_status_start_valid),
 
         .m_axis_status_finish_len(tx_sched_status_finish_len),
+        .m_axis_status_finish_queue(tx_sched_status_finish_queue),
         .m_axis_status_finish_tag(tx_sched_status_finish_tag),
         .m_axis_status_finish_valid(tx_sched_status_finish_valid)
     );
@@ -2491,15 +2506,18 @@ end else begin
 
     assign tx_sched_status_dequeue_empty = tx_status_dequeue_empty;
     assign tx_sched_status_dequeue_error = tx_status_dequeue_error;
+    assign tx_sched_status_dequeue_queue = tx_status_dequeue_queue;
     assign tx_sched_status_dequeue_tag = tx_status_dequeue_tag;
     assign tx_sched_status_dequeue_valid = tx_status_dequeue_valid;
 
     assign tx_sched_status_start_error = tx_status_start_error;
     assign tx_sched_status_start_len = tx_status_start_len;
+    assign tx_sched_status_start_queue = tx_status_start_queue;
     assign tx_sched_status_start_tag = tx_status_start_tag;
     assign tx_sched_status_start_valid = tx_status_start_valid;
 
     assign tx_sched_status_finish_len = tx_status_finish_len;
+    assign tx_sched_status_finish_queue = tx_status_finish_queue;
     assign tx_sched_status_finish_tag = tx_status_finish_tag;
     assign tx_sched_status_finish_valid = tx_status_finish_valid;
 
@@ -2593,15 +2611,18 @@ interface_tx_inst (
      */
     .m_axis_tx_status_dequeue_empty(tx_status_dequeue_empty),
     .m_axis_tx_status_dequeue_error(tx_status_dequeue_error),
+    .m_axis_tx_status_dequeue_queue(tx_status_dequeue_queue),
     .m_axis_tx_status_dequeue_tag(tx_status_dequeue_tag),
     .m_axis_tx_status_dequeue_valid(tx_status_dequeue_valid),
 
     .m_axis_tx_status_start_error(tx_status_start_error),
     .m_axis_tx_status_start_len(tx_status_start_len),
+    .m_axis_tx_status_start_queue(tx_status_start_queue),
     .m_axis_tx_status_start_tag(tx_status_start_tag),
     .m_axis_tx_status_start_valid(tx_status_start_valid),
 
     .m_axis_tx_status_finish_len(tx_status_finish_len),
+    .m_axis_tx_status_finish_queue(tx_status_finish_queue),
     .m_axis_tx_status_finish_tag(tx_status_finish_tag),
     .m_axis_tx_status_finish_valid(tx_status_finish_valid),
 

diff --git a/fpga/common/rtl/mqnic_interface_tx.v b/fpga/common/rtl/mqnic_interface_tx.v
@@ -85,15 +85,18 @@ module mqnic_interface_tx #
      */
     output wire                                         m_axis_tx_status_dequeue_empty,
     output wire                                         m_axis_tx_status_dequeue_error,
+    output wire [QUEUE_INDEX_WIDTH-1:0]                 m_axis_tx_status_dequeue_queue,
     output wire [REQ_TAG_WIDTH-1:0]                     m_axis_tx_status_dequeue_tag,
     output wire                                         m_axis_tx_status_dequeue_valid,
 
     output wire                                         m_axis_tx_status_start_error,
     output wire [DMA_CLIENT_LEN_WIDTH-1:0]              m_axis_tx_status_start_len,
+    output wire [QUEUE_INDEX_WIDTH-1:0]                 m_axis_tx_status_start_queue,
     output wire [REQ_TAG_WIDTH-1:0]                     m_axis_tx_status_start_tag,
     output wire                                         m_axis_tx_status_start_valid,
 
     output wire [DMA_CLIENT_LEN_WIDTH-1:0]              m_axis_tx_status_finish_len,
+    output wire [QUEUE_INDEX_WIDTH-1:0]                 m_axis_tx_status_finish_queue,
     output wire [REQ_TAG_WIDTH-1:0]                     m_axis_tx_status_finish_tag,
     output wire                                         m_axis_tx_status_finish_valid,
 
@@ -327,15 +330,18 @@ tx_engine_inst (
      */
     .m_axis_tx_status_dequeue_empty(m_axis_tx_status_dequeue_empty),
     .m_axis_tx_status_dequeue_error(m_axis_tx_status_dequeue_error),
+    .m_axis_tx_status_dequeue_queue(m_axis_tx_status_dequeue_queue),
     .m_axis_tx_status_dequeue_tag(m_axis_tx_status_dequeue_tag),
     .m_axis_tx_status_dequeue_valid(m_axis_tx_status_dequeue_valid),
 
     .m_axis_tx_status_start_error(m_axis_tx_status_start_error),
     .m_axis_tx_status_start_len(m_axis_tx_status_start_len),
+    .m_axis_tx_status_start_queue(m_axis_tx_status_start_queue),
     .m_axis_tx_status_start_tag(m_axis_tx_status_start_tag),
     .m_axis_tx_status_start_valid(m_axis_tx_status_start_valid),
 
     .m_axis_tx_status_finish_len(m_axis_tx_status_finish_len),
+    .m_axis_tx_status_finish_queue(m_axis_tx_status_finish_queue),
     .m_axis_tx_status_finish_tag(m_axis_tx_status_finish_tag),
     .m_axis_tx_status_finish_valid(m_axis_tx_status_finish_valid),
 

diff --git a/fpga/common/rtl/mqnic_tx_scheduler_block_rr.v b/fpga/common/rtl/mqnic_tx_scheduler_block_rr.v
@@ -114,15 +114,18 @@ module mqnic_tx_scheduler_block #
      */
     input  wire                          s_axis_tx_status_dequeue_empty,
     input  wire                          s_axis_tx_status_dequeue_error,
+    input  wire [QUEUE_INDEX_WIDTH-1:0]  s_axis_tx_status_dequeue_queue,
     input  wire [TX_REQ_TAG_WIDTH-1:0]   s_axis_tx_status_dequeue_tag,
     input  wire                          s_axis_tx_status_dequeue_valid,
 
     input  wire                          s_axis_tx_status_start_error,
     input  wire [DMA_LEN_WIDTH-1:0]      s_axis_tx_status_start_len,
+    input  wire [QUEUE_INDEX_WIDTH-1:0]  s_axis_tx_status_start_queue,
     input  wire [TX_REQ_TAG_WIDTH-1:0]   s_axis_tx_status_start_tag,
     input  wire                          s_axis_tx_status_start_valid,
 
     input  wire [DMA_LEN_WIDTH-1:0]      s_axis_tx_status_finish_len,
+    input  wire [QUEUE_INDEX_WIDTH-1:0]  s_axis_tx_status_finish_queue,
     input  wire [TX_REQ_TAG_WIDTH-1:0]   s_axis_tx_status_finish_tag,
     input  wire                          s_axis_tx_status_finish_valid,
 
@@ -279,15 +282,18 @@ tx_scheduler_inst (
      */
     .s_axis_tx_status_dequeue_empty(s_axis_tx_status_dequeue_empty),
     .s_axis_tx_status_dequeue_error(s_axis_tx_status_dequeue_error),
+    .s_axis_tx_status_dequeue_queue(s_axis_tx_status_dequeue_queue),
     .s_axis_tx_status_dequeue_tag(s_axis_tx_status_dequeue_tag),
     .s_axis_tx_status_dequeue_valid(s_axis_tx_status_dequeue_valid),
 
     .s_axis_tx_status_start_error(s_axis_tx_status_start_error),
     .s_axis_tx_status_start_len(s_axis_tx_status_start_len),
+    .s_axis_tx_status_start_queue(s_axis_tx_status_start_queue),
     .s_axis_tx_status_start_tag(s_axis_tx_status_start_tag),
     .s_axis_tx_status_start_valid(s_axis_tx_status_start_valid),
 
     .s_axis_tx_status_finish_len(s_axis_tx_status_finish_len),
+    .s_axis_tx_status_finish_queue(s_axis_tx_status_finish_queue),
     .s_axis_tx_status_finish_tag(s_axis_tx_status_finish_tag),
     .s_axis_tx_status_finish_valid(s_axis_tx_status_finish_valid),
 

diff --git a/fpga/common/rtl/mqnic_tx_scheduler_block_rr_tdma.v b/fpga/common/rtl/mqnic_tx_scheduler_block_rr_tdma.v
@@ -114,15 +114,18 @@ module mqnic_tx_scheduler_block #
      */
     input  wire                          s_axis_tx_status_dequeue_empty,
     input  wire                          s_axis_tx_status_dequeue_error,
+    input  wire [QUEUE_INDEX_WIDTH-1:0]  s_axis_tx_status_dequeue_queue,
     input  wire [TX_REQ_TAG_WIDTH-1:0]   s_axis_tx_status_dequeue_tag,
     input  wire                          s_axis_tx_status_dequeue_valid,
 
     input  wire                          s_axis_tx_status_start_error,
     input  wire [DMA_LEN_WIDTH-1:0]      s_axis_tx_status_start_len,
+    input  wire [QUEUE_INDEX_WIDTH-1:0]  s_axis_tx_status_start_queue,
     input  wire [TX_REQ_TAG_WIDTH-1:0]   s_axis_tx_status_start_tag,
     input  wire                          s_axis_tx_status_start_valid,
 
     input  wire [DMA_LEN_WIDTH-1:0]      s_axis_tx_status_finish_len,
+    input  wire [QUEUE_INDEX_WIDTH-1:0]  s_axis_tx_status_finish_queue,
     input  wire [TX_REQ_TAG_WIDTH-1:0]   s_axis_tx_status_finish_tag,
     input  wire                          s_axis_tx_status_finish_valid,
 
@@ -450,15 +453,18 @@ tx_scheduler_inst (
      */
     .s_axis_tx_status_dequeue_empty(s_axis_tx_status_dequeue_empty),
     .s_axis_tx_status_dequeue_error(s_axis_tx_status_dequeue_error),
+    .s_axis_tx_status_dequeue_queue(s_axis_tx_status_dequeue_queue),
     .s_axis_tx_status_dequeue_tag(s_axis_tx_status_dequeue_tag),
     .s_axis_tx_status_dequeue_valid(s_axis_tx_status_dequeue_valid),
 
     .s_axis_tx_status_start_error(s_axis_tx_status_start_error),
     .s_axis_tx_status_start_len(s_axis_tx_status_start_len),
+    .s_axis_tx_status_start_queue(s_axis_tx_status_start_queue),
     .s_axis_tx_status_start_tag(s_axis_tx_status_start_tag),
     .s_axis_tx_status_start_valid(s_axis_tx_status_start_valid),
 
     .s_axis_tx_status_finish_len(s_axis_tx_status_finish_len),
+    .s_axis_tx_status_finish_queue(s_axis_tx_status_finish_queue),
     .s_axis_tx_status_finish_tag(s_axis_tx_status_finish_tag),
     .s_axis_tx_status_finish_valid(s_axis_tx_status_finish_valid),