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Add make clean #824

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Nov 15, 2023
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3 changes: 3 additions & 0 deletions e2e/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -43,3 +43,6 @@ $(HAMMER_D_MK):
hammer-vlsi --obj_dir $(OBJ_DIR) -e $(ENV_YML) $(HAMMER_EXTRA_ARGS) build

-include $(HAMMER_D_MK)

clean:
rm -rf $(OBJ_DIR) hammer-vlsi-*.log
2 changes: 1 addition & 1 deletion hammer/synthesis/genus/__init__.py
Original file line number Diff line number Diff line change
Expand Up @@ -224,7 +224,7 @@ def init_environment(self) -> bool:
))

# Load input files and check that they are all Verilog.
if not self.check_input_files([".v", ".sv"]):
if not self.check_input_files([".v", ".sv", "vh"]):
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return False
# We are switching working directories and Genus still needs to find paths.
abspath_input_files = list(map(lambda name: os.path.join(os.getcwd(), name), self.input_files)) # type: List[str]
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