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feat: AIC and AII implementation #201

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2 changes: 1 addition & 1 deletion .pre-commit-config.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@ repos:
hooks:
- id: prettier
- repo: https://github.com/pre-commit/pre-commit-hooks
rev: v4.0.1
rev: v5.0.0
hooks:
- id: trailing-whitespace
- id: end-of-file-fixer
Expand Down
81 changes: 81 additions & 0 deletions insim/src/insim/aic.rs
Original file line number Diff line number Diff line change
@@ -0,0 +1,81 @@
use insim_core::binrw::{self, binrw};

use crate::identifiers::{PlayerId, RequestId};

#[derive(PartialEq, Eq, Clone, Hash)]
#[cfg_attr(feature = "serde", derive(serde::Serialize))]
#[non_exhaustive]
// FIXME: Needs manual BinRead and BinWrite impl
pub enum AiInputType {
Msx(u32),

Throttle(u32),

Brake(u32),

Chup(u32),

Chdn(u32),

Ignition(u32),

ExtraLight(u32),

HeadLights(u32),

Siren(u32),

Horn(u32),

Flash(u32),

Clutch(u32),

Handbrake(u32),

Indicators(u32),

Gear(u32),

Look(u32),

Pitspeed(u32),

TcDisable(u32),

FogRear(u32),

FogFront(u32),
}

impl Default for AiInputType {
fn default() -> Self {
Self::Msx(32768)
}
}

#[binrw]
#[derive(Debug, Clone, Default)]
#[cfg_attr(feature = "serde", derive(serde::Serialize))]
// FIXME: Needs manual BinRead and BinWrite impl
pub struct AiInputVal {
pub input: u8,
pub time: u8,
}

#[binrw]
#[derive(Debug, Clone, Default)]
#[cfg_attr(feature = "serde", derive(serde::Serialize))]
/// AI Input Control
pub struct Aic {
/// Non-zero if the packet is a packet request or a reply to a request
pub reqi: RequestId,

/// Set to choose 16-bit
pub plid: PlayerId,

// FIXME: Needs manual BinRead and BinWrite implementation
pub inputs: Vec<AiInputVal>,
}

impl_typical_with_request_id!(Aic);
70 changes: 70 additions & 0 deletions insim/src/insim/aii.rs
Original file line number Diff line number Diff line change
@@ -0,0 +1,70 @@
use bitflags::bitflags;
use insim_core::{
binrw::{self, binrw},
point::Point,
};

use crate::identifiers::{PlayerId, RequestId};

#[binrw]
#[derive(Debug, Clone, Default)]
#[cfg_attr(feature = "serde", derive(serde::Serialize))]
pub struct OsMain {
pub angvel: (f32, f32, f32),

pub heading: f32,

pub pitch: f32,

pub roll: f32,

pub accel: Point<f32>,

pub vel: Point<f32>,

pub pos: Point<i32>,
}

bitflags! {
/// Provides extended host information
#[binrw]
#[br(map = Self::from_bits_truncate)]
#[bw(map = |&x: &Self| x.bits())]
#[derive(PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Clone, Copy, Default)]
#[cfg_attr(feature = "serde", derive(serde::Serialize))]
pub struct AiFlags: u8 {
/// Detect if engine running
const IGNITION = (1 << 0);
/// Upshift currently held
const CHUP = (1 << 2);
/// Downshift currently held
const CHDN = (1 << 3);
}
}

#[binrw]
#[derive(Debug, Clone, Default)]
#[cfg_attr(feature = "serde", derive(serde::Serialize))]
/// AI Info
pub struct Aii {
/// Non-zero if the packet is a packet request or a reply to a request
pub reqi: RequestId,

/// Set to choose 16-bit
pub plid: PlayerId,

pub osmain: OsMain,

pub flags: AiFlags,

#[brw(pad_after = 2)]
pub gear: u8,

#[brw(pad_after = 8)]
pub rpm: f32,

#[brw(pad_after = 12)]
pub showlights: u32,
}

impl_typical_with_request_id!(Aii);
4 changes: 4 additions & 0 deletions insim/src/insim/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,8 @@
mod racelaps;

mod acr;
mod aic;
mod aii;
mod axi;
mod axm;
mod axo;
Expand Down Expand Up @@ -66,6 +68,8 @@ mod ver;
mod vtn;

pub use acr::{Acr, AcrResult};
pub use aic::{AiInputVal, Aic};
pub use aii::{AiFlags, Aii};
pub use axi::Axi;
pub use axm::{Axm, ObjectInfo, PmoAction, PmoFlags};
pub use axo::Axo;
Expand Down
12 changes: 10 additions & 2 deletions insim/src/insim/small.rs
Original file line number Diff line number Diff line change
@@ -1,10 +1,13 @@
use std::time::Duration;
use std::{ops::Deref, time::Duration};

use bitflags::bitflags;
use insim_core::binrw::{self, binrw, BinRead, BinWrite};

use super::{PlcAllowedCarsSet, VtnAction};
use crate::{identifiers::RequestId, Packet, WithRequestId};
use crate::{
identifiers::{PlayerId, RequestId},
Packet, WithRequestId,
};

bitflags! {
#[derive(PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Clone, Copy, Default)]
Expand Down Expand Up @@ -160,6 +163,9 @@ pub enum SmallType {

/// Set local vehicle lights
Lcl(LclFlags),

/// Get local AI information
Aii(PlayerId),
}

impl Default for SmallType {
Expand Down Expand Up @@ -275,6 +281,7 @@ impl BinRead for SmallType {
8 => Self::Alc(PlcAllowedCarsSet::from_bits_truncate(uval)),
9 => Self::Lcs(LcsFlags::from_bits_truncate(uval)),
10 => Self::Lcl(LclFlags::from_bits_truncate(uval)),
11 => Self::Aii(PlayerId(uval as u8)),
_ => {
return Err(binrw::Error::BadMagic {
pos,
Expand Down Expand Up @@ -307,6 +314,7 @@ impl BinWrite for SmallType {
SmallType::Alc(uval) => (8u8, uval.bits()),
SmallType::Lcs(uval) => (9u8, uval.bits()),
SmallType::Lcl(uval) => (10u8, uval.bits()),
SmallType::Aii(plid) => (11u8, (*plid.deref() as u32)),
};

discrim.write_options(writer, endian, ())?;
Expand Down
12 changes: 12 additions & 0 deletions insim/src/packet.rs
Original file line number Diff line number Diff line change
Expand Up @@ -284,6 +284,14 @@ pub enum Packet {
#[brw(magic = 67u8)]
Ipb(Ipb),

/// Instruction - Set AI control value
#[brw(magic = 68u8)]
Aic(Aic),

/// Information - AI information
#[brw(magic = 69u8)]
Aii(Aii),

/// Instruction - Ask the LFS World relay if we are an admin
#[brw(magic = 250u8)]
RelayArq(Arq),
Expand Down Expand Up @@ -385,6 +393,8 @@ impl Packet {
Packet::Csc(_) => 20,
Packet::Cim(_) => 8,
Packet::Mal(_) => 12,
Packet::Aic(i) => 4 + (i.inputs.len() * 4),
Packet::Aii(_) => 96,
Packet::RelayHos(i) => 4 + (i.hinfo.len() * 40),
Packet::RelaySel(_) => 68,
_ => {
Expand Down Expand Up @@ -508,6 +518,8 @@ impl WithRequestId for Packet {
Packet::Mal(i) => i.reqi = reqi.into(),
Packet::Plh(i) => i.reqi = reqi.into(),
Packet::Ipb(i) => i.reqi = reqi.into(),
Packet::Aic(i) => i.reqi = reqi.into(),
Packet::Aii(i) => i.reqi = reqi.into(),
Packet::RelayArq(i) => i.reqi = reqi.into(),
Packet::RelayArp(i) => i.reqi = reqi.into(),
Packet::RelayHlr(i) => i.reqi = reqi.into(),
Expand Down
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