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udi-speedb committed Apr 5, 2022
1 parent 916f43d commit e7c89aa
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Showing 3 changed files with 1 addition and 3 deletions.
2 changes: 1 addition & 1 deletion cache/lru_cache.h
Original file line number Diff line number Diff line change
Expand Up @@ -393,7 +393,7 @@ class ALIGN_AS(CACHE_LINE_SIZE) LRUCacheShard final : public CacheShard {
// Dummy head of LRU list.
// lru.prev is newest entry, lru.next is oldest entry.
// LRU contains items which can be evicted, ie reference only by cache
LRUH andle lru_;
LRUHandle lru_;

// Pointer to head of low-pri pool in LRU list.
LRUHandle* lru_low_pri_;
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1 change: 0 additions & 1 deletion cache/sharded_cache.cc
Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,6 @@ inline uint32_t HashSlice(const Slice& s) {

ShardedCache::ShardedCache(size_t capacity, int num_shard_bits,
bool strict_capacity_limit,
bool spdb_cache_counters,
std::shared_ptr<MemoryAllocator> allocator)
: Cache(std::move(allocator)),
shard_mask_((uint32_t{1} << num_shard_bits) - 1),
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1 change: 0 additions & 1 deletion cache/sharded_cache.h
Original file line number Diff line number Diff line change
Expand Up @@ -73,7 +73,6 @@ class CacheShard {
class ShardedCache : public Cache {
public:
ShardedCache(size_t capacity, int num_shard_bits, bool strict_capacity_limit,
bool spdb_cache_counters,
std::shared_ptr<MemoryAllocator> memory_allocator = nullptr);
virtual ~ShardedCache() = default;
virtual CacheShard* GetShard(uint32_t shard) = 0;
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