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[FIX] Fix bcm pl011 UART #168

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[FIX] Fix bcm pl011 UART #168

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09a20f9
libplatsupport: Fix bcm pl011 UART
FelixSchladt Aug 29, 2023
e456c24
libplatsupport: fix typo
FelixSchladt Sep 7, 2023
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25 changes: 14 additions & 11 deletions libplatsupport/src/mach/bcm/pl011_uart.c
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Original file line number Diff line number Diff line change
Expand Up @@ -61,6 +61,8 @@ pl011_regs_t;
/* IMSC register */
#define IMSC_RXIM BIT(4)
#define IMSC_TXIM BIT(5)
#define IMSC_RTIM BIT(6)
#define IMSC_OEIM BIT(10)

/* ICR register */
#define ICR_RXIC BIT(4)
Expand Down Expand Up @@ -96,16 +98,18 @@ static inline void pl011_uart_disable_fifo(ps_chardevice_t *dev)
r->lcrh &= ~LCRH_FEN;
}

static inline void pl011_uart_enable_rx_irq(ps_chardevice_t *dev)
static inline void pl011_uart_enable_irqs(ps_chardevice_t *dev)
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{
pl011_regs_t *r = pl011_uart_get_priv(dev);
r->imsc |= IMSC_RXIM;
r->imsc |= IMSC_RXIM; // Receive interrupt mask
r->imsc |= IMSC_RTIM; // Receive timeout interrupt mask
r->imsc |= IMSC_OEIM; // Overrun error interrupt mask
}

static inline void pl011_uart_disable_rx_irq(ps_chardevice_t *dev)
static inline void pl011_uart_disable_irqs(ps_chardevice_t *dev)
{
pl011_regs_t *r = pl011_uart_get_priv(dev);
r->imsc &= ~IMSC_RXIM;
r->imsc = 0;
}

static inline void pl011_uart_wait_busy(ps_chardevice_t *dev)
Expand All @@ -128,7 +132,7 @@ static int pl011_uart_cr_configure(ps_chardevice_t *dev)
uint32_t val = r->cr;

val |= CR_TXE; // Transmit enable
val |= CR_RXE; // Teceive enable
val |= CR_RXE; // Receive enable
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r->cr = val;

Expand Down Expand Up @@ -193,8 +197,7 @@ static int pl011_uart_configure(ps_chardevice_t *dev)
pl011_uart_disable(dev);

// Disable RX/all interrupts
//pl011_uart_disable_rx_irq(dev);
r->imsc = 0x7f1;
pl011_uart_disable_irqs(dev);

// Wait till UART is not busy anymore
pl011_uart_wait_busy(dev);
Expand Down Expand Up @@ -227,14 +230,14 @@ static int pl011_uart_configure(ps_chardevice_t *dev)
*
*/
// Enable FIFO
//pl011_uart_enable_fifo(dev);
pl011_uart_enable_fifo(dev);
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I'm not convinced that the problem mentioned in the comment is properly addressed. I am afraid that enabling FIFOs is just a work-around for an unfixed bug, probably caused by the original's code assumptions of the current state of the UART or initialisation.

Have you tried fully configuring the UART and setting all registers, and clearing any pending IRQs and errors at init?

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I tested the current state again today and it is working fine.

Sending single bytes is not an issue.
For testing I did setup a simple uart echo server which is interrupt triggered.

2024-03-15_13-43

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Please print something out at every receive interrupt and check that you don't get any when no input is given.

Or keep a counter and print out the counter value too.


// Enable interrupts
pl011_uart_enable_irqs(dev);

// Enable UART
pl011_uart_enable(dev);

// Enable RX interrupt
pl011_uart_enable_rx_irq(dev);

return 0;
}

Expand Down