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hal: rearrange code, move
src
into path allwinner-hal
Signed-off-by: Zhouqi Jiang <[email protected]>
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[package] | ||
name = "allwinner-hal" | ||
version = "0.0.0" | ||
edition = "2021" | ||
description = "Allwinner SoC driver support" | ||
authors = [ | ||
"Luo Jia <[email protected]>", | ||
"Gao Chengbo <[email protected]>", | ||
] | ||
repository = "https://github.com/rustsbi/allwinner-hal" | ||
documentation = "https://docs.rs/allwinner-hal" | ||
license = "MulanPSL-2.0 OR MIT" | ||
readme = "README.md" | ||
keywords = ["hal", "allwinner"] | ||
categories = ["os", "embedded", "hardware-support", "no-std"] | ||
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# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html | ||
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[dependencies] | ||
volatile-register = "0.2.1" | ||
embedded-hal = "1.0.0" | ||
embedded-io = "0.6.1" | ||
embedded-time = "0.12.1" | ||
uart16550 = "0.0.1" | ||
plic = "0.0.2" | ||
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[dev-dependencies] | ||
memoffset = "0.8" | ||
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[features] | ||
default = ["d1"] | ||
# D1-like chips: D1-H, D1s, F133. | ||
d1 = [] | ||
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[workspace] | ||
resolver = "2" | ||
members = [ | ||
"allwinner-hal", | ||
"allwinner-rt", | ||
"allwinner-rt/macros", | ||
"examples/nezha-d1", | ||
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[package] | ||
name = "allwinner-hal" | ||
version = "0.0.0" | ||
edition = "2021" | ||
description = "Allwinner SoC driver support" | ||
authors = [ | ||
"Luo Jia <[email protected]>", | ||
"Gao Chengbo <[email protected]>", | ||
] | ||
repository = "https://github.com/rustsbi/allwinner-hal" | ||
documentation = "https://docs.rs/allwinner-hal" | ||
license = "MulanPSL-2.0 OR MIT" | ||
readme = "README.md" | ||
keywords = ["hal", "allwinner"] | ||
categories = ["os", "embedded", "hardware-support", "no-std"] | ||
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# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html | ||
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[dependencies] | ||
volatile-register = "0.2.1" | ||
embedded-hal = "1.0.0" | ||
embedded-io = "0.6.1" | ||
embedded-time = "0.12.1" | ||
uart16550 = "0.0.1" | ||
plic = "0.0.2" | ||
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[dev-dependencies] | ||
memoffset = "0.8" | ||
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[features] | ||
default = ["d1"] | ||
# D1-like chips: D1-H, D1s, F133. | ||
d1 = [] |
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# allwinner-hal | ||
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[![crates.io](https://img.shields.io/crates/v/allwinner-hal.svg)](https://crates.io/crates/allwinner-hal) | ||
[![Documentation](https://docs.rs/allwinner-hal/badge.svg)](https://docs.rs/allwinner-hal) | ||
![License](https://img.shields.io/crates/l/allwinner-hal.svg) | ||
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全志芯片组件化外设驱动;外设包括DDR控制器。 | ||
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## 支持列表 | ||
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组件化外设驱动可根据外设基地址提供驱动支持,这要求外设的设计(寄存器定义和功能等)相同; | ||
大多数情况下,外设IP核相同就能满足以上条件。 | ||
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按此要求,虽然全志系列芯片大部分外设IP核都是共享的,但本项目只测试了一部分芯片的兼容性。 | ||
经过测试能够运行本项目的芯片如下。 | ||
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| 系列* | CCU | GPIO | SPI | UART | | ||
|:-----|:----|:----|:----|:----| | ||
| D1系列 | ○ | ○ | ○ | ○ | | ||
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✓:可运行,功能完整 | ||
○:可运行,详细功能仍需完善 | ||
×:暂未支持 | ||
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*全志芯片中有一部分型号的外设基地址布局相同,即使其中的处理器核可能不相同。 | ||
本项目称这些芯片为一个系列,并以系列中首个发布的芯片型号命名。 | ||
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理论上兼容,但尚未经过测试的芯片型号如下: | ||
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- D1系列:D1s, F133, V853, R128 | ||
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## 许可协议 | ||
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本项目使用MIT和Mulan-PSL v2.0双许可协议。 | ||
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## 参考资料 | ||
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以下资料提供了全志芯片驱动的参考设计或社区设计,供贡献者参考。 | ||
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- RT-Thread驱动:https://gitee.com/rtthread/rt-thread/tree/master/bsp/allwinner/libraries/sunxi-hal/hal/source | ||
- TinyKasKit项目:https://github.com/YuzukiHD/TinyKasKit |
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