Bring in remaining changes from master

README.md

@@ -1,10 +1,10 @@
 RISC-V Debug Specification
 ==========================
 
-The current master branch is v1.0.0-stable.
+The current master branch is v1.0.0-frozen.
 
 You may be looking for one of the following pre-built PDFs:
-* [Latest stable](https://github.com/riscv/riscv-debug-spec/blob/master/riscv-debug-stable.pdf)
+* [Latest frozen](https://github.com/riscv/riscv-debug-spec/blob/master/riscv-debug-frozen.pdf)
 * [Latest release](https://github.com/riscv/riscv-debug-spec/blob/release/riscv-debug-release.pdf)
 
 Build Instructions

Sdtrig.adoc

@@ -284,6 +284,36 @@ constant data.
 . The prefetch instructions don't match at all.
 ====
 
+==== Address Matches
+
+For address matches without a mask, {csr-tdata2} must be able to hold all valid
+addresses in all supported translation modes. That means that after writing any
+of these valid addresses, the exact same value XLEN-wide value is read back,
+including any high bits. An implementation may be able to optimize the storage
+required, depending on the widest addresses it supports.
+
+[NOTE]
+====
+If physical addresses are less than XLEN bits wide, they are zero-extended.
+If virtual addresses are less than XLEN bits wide, they are sign-extended.
+{csr-tdata2} must be implemented with enough bits of storage to represent
+the full range of supported physical and virtual address values when read by
+software and used by hardware.
+====
+
+===== Invalid Addresses
+
+If {csr-tdata2} can hold any invalid addresses, then writes of an
+invalid address that can not be represented as-is should be converted to
+a different invalid address that can be represented.
+
+For invalid instruction fetch addresses and load and store effective addresses,
+the compare value may be changed to a different invalid address.
+
+In addition, an implementation may choose to inhibit all trigger matching
+against invalid addresses, especially if there is no support for storage of any
+invalid address values in tdata2.
+
 [[multistate]]
 === Multiple State Change Instructions
 
@@ -305,10 +335,11 @@ and then executing it again leaves the hart in a state closely
 resembling the state it would have been in if the instruction had only
 been executed once.
 
-=== Trigger Registers
+=== Trigger Module Registers
 
 These registers are CSRs, accessible using the RISC-V `csr` opcodes and
-optionally also using abstract debug commands.
+optionally also using abstract debug commands. They are the only mechanism
+to access the triggers.
 
 Almost all trigger functionality is optional. All `tdata` registers
 follow write-any-read-legal semantics. If a debugger writes an
@@ -336,7 +367,7 @@ fire in the current privilege mode must use this same sequence to
 restore the triggers. This avoids the problem of a partially written
 trigger firing at a different time than is expected.
 
-Attempts to access an unimplemented Trigger Register raise an illegal
+Attempts to access an unimplemented Trigger Module Register raise an illegal
 instruction exception.
 
 include::build/hwbp_registers.adoc[]

introduction.adoc

@@ -166,7 +166,7 @@ https://github.com/riscv/riscv-debug-spec/pull/405[#405]
 https://github.com/riscv/riscv-debug-spec/pull/414[#414]
 . Address triggers ({csr-mcontrol}) may fire on any accessed address.
 https://github.com/riscv/riscv-debug-spec/pull/421[#421]
-. All trigger registers (<<tab:trigger>>) are optional. https://github.com/riscv/riscv-debug-spec/pull/431[#431]
+. All Trigger Module registers (<<tab:trigger>>) are optional. https://github.com/riscv/riscv-debug-spec/pull/431[#431]
 . When extending IR, {dtm-bypass} still is all ones.
 https://github.com/riscv/riscv-debug-spec/pull/437[#437]
 . {dcsr-ebreaks} and {dcsr-ebreaku} are WARL. https://github.com/riscv/riscv-debug-spec/pull/458[#458]

riscv-debug-header.adoc

@@ -2,10 +2,10 @@
 = The RISC-V Debug Specification
 :description: RISC-V Debug Specification
 :company: RISC-V.org
-:authors: Editors: Paul Donahue <[email protected]>, Ventana Micro Systems, Tim Newsome <tim@sifive.com>, SiFive, Inc.
-:revdate: Revised 20231107
-:revnumber: 20231107
-//:revremark: Pre-release version
+:authors: Editors: Paul Donahue <[email protected]>, Ventana Micro Systems, Tim Newsome <tim@casualhacker.net>, Individual Member
+:revdate: Revised 2024-01-25
+:revnumber: 1.0.0-rc0
+:revremark: Frozen
 :url-riscv: http://riscv.org
 :doctype: book
 :colophon:
@@ -52,7 +52,12 @@ endif::[]
 
 [WARNING]
 ====
-This stable specification might change before being accepted as standard. We're trying to only make backwards-compatible changes, but sometimes it's unavoidable to change a corner case. If you implement this document, please keep an eye on https://github.com/riscv/riscv-debug-spec[the github repository] for changes that might affect your implementation.
+*This specification is Frozen.*
+
+Change is extremely unlikely. A high threshold will be used, and a change
+will only occur because of some truly critical issue being identified during
+the public review cycle. Any other desired or needed changes can be the
+subject of a follow-on new extension.
 ====
 
 Contributors to all versions of the spec in alphabetical order (please