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Don't allow tdata2 to be smaller for address matches.
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This led to endless discussion about what happens when matching invalid
addresses. This is on the critical path for Architectural Review
approval, which is more important than allowing an implementation to
save a few gates on triggers that match on addresses but not on data.
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timsifive committed Dec 4, 2023
1 parent 4f58366 commit be76e08
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Showing 2 changed files with 2 additions and 12 deletions.
2 changes: 2 additions & 0 deletions introduction.tex
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Expand Up @@ -236,6 +236,8 @@ \subsubsection{Incompatible Changes During 1.0 Stable}
the {\tt progbuf} registers. \PR{731}
\item \RcsrTcontrol fields apply to all traps, not just breakpoint traps. This
reverts \PR{723}. \PR{880}
\item \RcsrTdataTwo cannot be limited to only holding addresses, even if only
addresses can be matched. \PR{919}
\end{steps}

\section{About This Document}
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12 changes: 0 additions & 12 deletions xml/hwbp_registers.xml
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Expand Up @@ -310,12 +310,6 @@
Table~\ref{tab:hwbp_timing}, both timings should be supported on load
address triggers.

This trigger type may be limited to address comparisons (\FcsrMcontrolSelect is
always 0) only. If that is the case and masking is not supported (match
values 4, 5, 12, 13), then \RcsrTdataTwo must be able to
hold all valid virtual addresses but it need not be capable of holding
other values.

The Privileged Spec says that breakpoint exceptions that occur on
instruction fetches, loads, or stores update the {\tt tval} CSR
with either zero or the faulting virtual address. The faulting
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A chain of triggers must only fire if every trigger in the chain was
matched by the same instruction.

This trigger type may be limited to address comparisons (\FcsrMcontrolSixSelect is
always 0) only. If that is the case and masking is not supported (match
values 4, 5, 12, 13), then \RcsrTdataTwo must be able to
hold all valid virtual addresses but it need not be capable of holding
other values.

The Privileged Spec says that breakpoint exceptions that occur on
instruction fetches, loads, or stores update the {\tt tval} CSR
with either zero or the faulting virtual address. The faulting
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