Add changes from #917.

Sdtrig.adoc

@@ -305,7 +305,7 @@ and then executing it again leaves the hart in a state closely
 resembling the state it would have been in if the instruction had only
 been executed once.
 
-=== Trigger Registers
+=== Trigger Module Registers
 
 These registers are CSRs, accessible using the RISC-V `csr` opcodes and
 optionally also using abstract debug commands.
@@ -336,7 +336,7 @@ fire in the current privilege mode must use this same sequence to
 restore the triggers. This avoids the problem of a partially written
 trigger firing at a different time than is expected.
 
-Attempts to access an unimplemented Trigger Register raise an illegal
+Attempts to access an unimplemented Trigger Module Register raise an illegal
 instruction exception.
 
 include::build/hwbp_registers.adoc[]

introduction.adoc

@@ -166,7 +166,7 @@ https://github.com/riscv/riscv-debug-spec/pull/405[#405]
 https://github.com/riscv/riscv-debug-spec/pull/414[#414]
 . Address triggers ({csr-mcontrol}) may fire on any accessed address.
 https://github.com/riscv/riscv-debug-spec/pull/421[#421]
-. All trigger registers (<<tab:trigger>>) are optional. https://github.com/riscv/riscv-debug-spec/pull/431[#431]
+. All Trigger Module registers (<<tab:trigger>>) are optional. https://github.com/riscv/riscv-debug-spec/pull/431[#431]
 . When extending IR, {dtm-bypass} still is all ones.
 https://github.com/riscv/riscv-debug-spec/pull/437[#437]
 . {dcsr-ebreaks} and {dcsr-ebreaku} are WARL. https://github.com/riscv/riscv-debug-spec/pull/458[#458]