[vector-crypto-extra] typo fix and improvements

riscv · Feb 1, 2024 · 1bfa9e3 · 1bfa9e3
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Showing 6 changed files with 13 additions and 13 deletions.
diff --git a/doc/vector-extra/insns/vclmul-32e.adoc b/doc/vector-extra/insns/vclmul-32e.adoc
@@ -51,7 +51,7 @@ Arguments::
 
 | `vs1`/`rs1` | input  | multiplier
 | `vs2`       | input  | multiplicand
-| `vd`        | output | lower part of carry-less 
+| `vd`        | output | lower part of carry-less multiply 
 |===
 
 [NOTE]
@@ -70,7 +70,7 @@ significant SEW bits of the carry-less product.
 [NOTE]
 ====
 The 32-bit carryless multiply instructions can be used for implementing GCM in the absence of the `zvkg` extension.
-In particular for implementation with `ELEN=32` where `Zvkg` cannot be implemented.
+In particular for implementation with `ELEN=32` where `Zvkg` cannot be implemented. 
 It can also be used to speed-up CRC evaluation.
 ====
 

diff --git a/doc/vector-extra/insns/vclmulh-32e.adoc b/doc/vector-extra/insns/vclmulh-32e.adoc
@@ -51,7 +51,7 @@ Arguments::
 
 | `vs1`/`rs1` | input  | multiplier
 | `vs2`       | input  | multiplicand
-| `vd`        | output | upper part of carry-less 
+| `vd`        | output | upper part of carry-less multiply 
 |===
 
 [NOTE]

diff --git a/doc/vector-extra/riscv-crypto-vector-extra-inst-table.adoc b/doc/vector-extra/riscv-crypto-vector-extra-inst-table.adoc
@@ -27,7 +27,7 @@ The new/modified encoding are in bold and underlined.
 |100000  | | | |            | 100000 |V| | vsm3me       | 100000 | | |
 | 100001 | | | |            | 100001 |V| | vsm4k.vi     | 100001 | | |
 | 100010 | | | |            | 100010 |V| | vaesfk1.vi   | 100010 | | |
-| 100011 | | | |            | 100011 | | | __**vghsh.vs**__ | 100011 | | |
+| 100011 | | | |            | 100011 |V| | __**vghsh.vs**__ | 100011 | | |
 | 100100 | | | |            | 100100 | | |              | 100100 | | |
 | 100101 | | | |            | 100101 | | |              | 100101 | | |
 | 100110 | | | |            | 100110 | | |              | 100110 | | |

diff --git a/doc/vector-extra/riscv-crypto-vector-extra-introduction.adoc b/doc/vector-extra/riscv-crypto-vector-extra-introduction.adoc
@@ -3,8 +3,8 @@
 
 This document describes the proposed _vector_ _extra_ cryptography
 extensions for RISC-V.
-Those extensions extends the _vector_ cryptography extensions for RISC-V,
-providing extra feature not mandatory for a high performace implementation but which
+Those extensions extend the _vector_ cryptography extensions for RISC-V,
+providing extra features not mandatory for a high performace implementation but which
 can help further improve the efficiency of the algorithms that use them.
 All instructions proposed here are based on the Vector registers.
 
diff --git a/doc/vector-extra/riscv-crypto-vector-extra-zvbc32e.adoc b/doc/vector-extra/riscv-crypto-vector-extra-zvbc32e.adoc
@@ -16,8 +16,8 @@ Note:: The extension `Zvbc32e` is independent from `Zvbc` which defines the same
 |===
 |Mnemonic
 |Instruction
-| vclmul.[vv,vx]     | <<insns-vclmul-32e>>
-| vclmulh.[vv,vx]    | <<insns-vclmulh-32e>>
+| `vclmul.[vv,vx]`     | <<insns-vclmul-32e>>
+| `vclmulh.[vv,vx]`    | <<insns-vclmulh-32e>>
 
 |===
 
diff --git a/doc/vector-extra/riscv-crypto-vector-extra-zvkgs.adoc b/doc/vector-extra/riscv-crypto-vector-extra-zvkgs.adoc
@@ -6,11 +6,11 @@
 Instructions to enable the efficient implementation of parallel versions of GHASH~H~ which is used in Galois/Counter Mode (GCM) and
 Galois Message Authentication Code (GMAC).
 
-The instructions inherit the same constraints (element group size, data independent execution timing and `vl`/`vstart` multiple constraints).
+The instructions inherit the same constraints as the ones mandated for `Zvkg` instructions: (element group size, data independent execution timing and `vl`/`vstart` multiple constraints).
 
-All of these instructions work on 128-bit element groups comprised of four 32-bit elements.
+All of these instructions work on 128-bit element groups comprised of four 32-bit elements, in element group parlance `EGS=4`, `EGW=128` and the instructions are only defined for `SEW=32`.
 
-To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing.
+To help avoid side-channel timing attacks, these instructions shall always be implemented with data-independent timing.
 
 The number of element groups to be processed is `vl`/`EGS`.
 `vl` must be set to the number of `SEW=32` elements to be processed and
@@ -25,8 +25,8 @@ Likewise, `vstart` must be a multiple of `EGS=4`.
 |EGW
 |Mnemonic
 |Instruction
-| 32 | 128 | vghsh.vs | <<insns-vghsh-vs>>
-| 32 | 128 | vgmul.vs | <<insns-vgmul-vs>>
+| 32 | 128 | `vghsh.vs` | <<insns-vghsh-vs>>
+| 32 | 128 | `vgmul.vs` | <<insns-vgmul-vs>>
 
 |===