Merge pull request #49 from tariqkurd-repo/fix_issue_42

Fix issue 42
riscv · Jan 25, 2024 · 449e25a · 449e25a
2 parents 0c7d900 + 8e81c8e
commit 449e25a
Showing 1 changed file with 3 additions and 2 deletions.
diff --git a/src/riscv-legacy-integration.adoc b/src/riscv-legacy-integration.adoc
@@ -189,8 +189,9 @@ When the XLEN-bit alias is used by <<CSRRW>>:
 * Only XLEN bits from the *x* source are written to the capability address
 field.
     ** The tag and metadata are updated as specified in <<extended_CSR_writing>>.
-* Only XLEN bits are read from the capability address field, which is zero
-extended to the destination *x* register.
+* Only XLEN bits are read from the capability address field, which are extended
+to XLENMAX bits according to cite:[riscv-priv-spec] _(3.1.6.2. Base ISA Control in 
+mstatus Register)_ and are then written to the destination *x* register.
 
 When the CLEN-bit alias is used by <<CSRRW>>: