Add The RISC-V Reader: An Open Architecture Atlas

README.md

@@ -59,6 +59,7 @@ For those with little or no knowledge of digital logic design. After studying th
 | Resource  |  Author(s) | Description  | Access | Date added |
 |---|---|---|---|---|
 |  <span id="digital-design">**Digital Design and Computer Architecture RISC-V edition**</span> (good starting point) | Sarah L. Harris, David M. Harris   | Covers the foundational knowledge of digital logic design and segues smoothly into RISC-V Processor implementation. <i><br><br><ins>Topics</ins>: Number systems and digital representation, Semiconductors and transistors, Logic gates and Digital design, C Programming, RISC-V architecture, RISC-V assembly, Memory systems, Embedded I/O systems</i> | <a href="https://www.amazon.com/Digital-Design-Computer-Architecture-RISC-V/dp/0128200642/ref=sr_1_5?crid=1Y6VGCXHTB99I&keywords=digital+design+and+computer+architecture&qid=1659609065&sprefix=digital+design+and+computer+architecture%2Caps%2C135&sr=8-5" target="_blank">[Amazon book link]</a>| 2024-01-10 |
+|  <span id="digital-design">**The RISC-V Reader: An Open Architecture Atlas**</span> | David Patterson, Andrew Waterman| A beginner-friendly introduction to the RISC-V instruction set architecture as readers can start programming after the 2nd chapter. <i><br><br><ins>Topics</ins>: Computer architecture, RISC-V Instruction Set Architecture (ISA)</i> | <a href="http://www.riscbook.com/" target="_blank">[Available in Chineses, Japanese, Spanish, Portuguese and Korean]</a>| 2024-03-05 |
 | **Nand2Tetris** (optional) | Noam Nisan, Shimon Schocken | A free hands-on tutorial on building a general-purpose computer from logic gates using a hardware simulator. <i><br><br><ins>Topics</ins>: Logic gates<i>|<a href="https://www.nand2tetris.org/" target="_blank">[webpage]</a> | 2024-01-10 |
 |<span id="bruno-levy-episode-1">**learn-FPGA episode I: from blinky to RISC-V**</span>|[BrunoLevy](https://github.com/BrunoLevy)|A beginner's introduction to the digital design of a RISC-V softcore on FPGAs. Episode I gently starts from a very basic blinker in Verilog and morphs it step by step into a basic yet fully functional RISC-V SoC. It also explains how to write programs in C and assembly for the SoC.<i><br><br><ins>Topics</ins>: Digital design, FPGA, C Programming, RISC-V assembly<br><ins>Requirement</ins>: Basic knowledge of Verilog</i>|<a href="https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/README.md" target="_blank">[GitHub]</a>| 2024-01-10 |
 |**Hands-on RISC-V Processor Design**|[Rahul Behl](https://github.com/raulbehl)|This practical tutorial offers a deep dive into the world of computer architecture and processor design, with a specific focus on the RISC-V Instruction Set Architecture (ISA).<i><br><br><ins>Topics</ins>: Computer architecture, Processor design, RISC-V Instruction Set Architecture (ISA), SystemVerilog, RISC-V assembly<br><ins>Requirements</ins>: SystemVerilog but not necessary</i>|<a href="https://quicksilicon.in/course/riscv" target="_blank">[webpage]</a> | 2024-01-10 |