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add support for rve #280

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add support for rve #280

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8 changes: 8 additions & 0 deletions dummy_payload/dummy_entry.S
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Original file line number Diff line number Diff line change
Expand Up @@ -9,13 +9,21 @@ _start:
1:
lbu a0, (s0)
beqz a0, 1f
#ifdef __riscv_e
li t0, SBI_CONSOLE_PUTCHAR
#else
li a7, SBI_CONSOLE_PUTCHAR
#endif
ecall
add s0, s0, 1
j 1b

1:
#ifdef __riscv_e
li t0, SBI_SHUTDOWN
#else
li a7, SBI_SHUTDOWN
#endif
ecall

.data
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6 changes: 6 additions & 0 deletions machine/mentry.S
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Original file line number Diff line number Diff line change
Expand Up @@ -125,6 +125,7 @@ trap_vector:
csrrw t0, mscratch, x0 # t0 <- user sp
STORE a4,14*REGBYTES(sp)
STORE a5,15*REGBYTES(sp)
#ifndef __riscv_e
STORE a6,16*REGBYTES(sp)
STORE a7,17*REGBYTES(sp)
STORE s2,18*REGBYTES(sp)
Expand All @@ -141,6 +142,7 @@ trap_vector:
STORE t4,29*REGBYTES(sp)
STORE t5,30*REGBYTES(sp)
STORE t6,31*REGBYTES(sp)
#endif
STORE t0, 2*REGBYTES(sp) # sp

#ifndef __riscv_flen
Expand Down Expand Up @@ -175,6 +177,7 @@ restore_regs:
LOAD a3,13*REGBYTES(sp)
LOAD a4,14*REGBYTES(sp)
LOAD a5,15*REGBYTES(sp)
#ifndef __riscv_e
LOAD a6,16*REGBYTES(sp)
LOAD a7,17*REGBYTES(sp)
LOAD s2,18*REGBYTES(sp)
Expand All @@ -191,6 +194,7 @@ restore_regs:
LOAD t4,29*REGBYTES(sp)
LOAD t5,30*REGBYTES(sp)
LOAD t6,31*REGBYTES(sp)
#endif
LOAD sp, 2*REGBYTES(sp)
mret

Expand Down Expand Up @@ -237,6 +241,7 @@ do_reset:
li x13, 0
li x14, 0
li x15, 0
#ifndef __riscv_e
li x16, 0
li x17, 0
li x18, 0
Expand All @@ -253,6 +258,7 @@ do_reset:
li x29, 0
li x30, 0
li x31, 0
#endif
csrw mscratch, x0

#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
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8 changes: 6 additions & 2 deletions pk/entry.S
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Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,7 @@
STORE x13,13*REGBYTES(x2)
STORE x14,14*REGBYTES(x2)
STORE x15,15*REGBYTES(x2)
#ifndef __riscv_e
STORE x16,16*REGBYTES(x2)
STORE x17,17*REGBYTES(x2)
STORE x18,18*REGBYTES(x2)
Expand All @@ -35,18 +36,19 @@
STORE x29,29*REGBYTES(x2)
STORE x30,30*REGBYTES(x2)
STORE x31,31*REGBYTES(x2)
#endif

# get sr, epc, badvaddr, cause
csrrw t0,sscratch,x0
csrr s0,sstatus
csrr t1,sepc
csrr t2,stval
csrr t3,scause
csrr s1,scause
STORE t0,2*REGBYTES(x2)
STORE s0,32*REGBYTES(x2)
STORE t1,33*REGBYTES(x2)
STORE t2,34*REGBYTES(x2)
STORE t3,35*REGBYTES(x2)
STORE s1,35*REGBYTES(x2)
1:
.endm

Expand Down Expand Up @@ -91,6 +93,7 @@ start_user:
LOAD x13,13*REGBYTES(a0)
LOAD x14,14*REGBYTES(a0)
LOAD x15,15*REGBYTES(a0)
#ifndef __riscv_e
LOAD x16,16*REGBYTES(a0)
LOAD x17,17*REGBYTES(a0)
LOAD x18,18*REGBYTES(a0)
Expand All @@ -107,6 +110,7 @@ start_user:
LOAD x29,29*REGBYTES(a0)
LOAD x30,30*REGBYTES(a0)
LOAD x31,31*REGBYTES(a0)
#endif
# restore a0 last
LOAD x10,10*REGBYTES(a0)

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5 changes: 5 additions & 0 deletions pk/handlers.c
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Original file line number Diff line number Diff line change
Expand Up @@ -80,8 +80,13 @@ static void handle_fault_store(trapframe_t* tf)

static void handle_syscall(trapframe_t* tf)
{
#ifdef __riscv_e
tf->gpr[10] = do_syscall(tf->gpr[10], tf->gpr[11], tf->gpr[12], tf->gpr[13],
tf->gpr[14], tf->gpr[15], tf->gpr[5]);
#else
tf->gpr[10] = do_syscall(tf->gpr[10], tf->gpr[11], tf->gpr[12], tf->gpr[13],
tf->gpr[14], tf->gpr[15], tf->gpr[17]);
#endif
tf->epc += 4;
}

Expand Down