target/riscv: Add Nuclei custom float-pstinc support

riscv-mcu · Oct 23, 2023 · 4fa8d55 · 4fa8d55
1 parent c4c858a
commit 4fa8d55
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diff --git a/target/riscv/Xxlcz.decode b/target/riscv/Xxlcz.decode
@@ -79,6 +79,12 @@ xl_sw           0111  ...  ..... ..... 001 ..... 1111011 @s8
 xl_lwu          1000  ........   ..... 001 ..... 1111011 @i8
 xl_ld           1001  ........   ..... 001 ..... 1111011 @i8
 xl_sd           1010  ...  ..... ..... 001 ..... 1111011 @s8
+xl_flh          0101  ...  ..... ..... 101 ..... 1111011 @i8
+xl_flw          0110  ...  ..... ..... 101 ..... 1111011 @i8
+xl_fld          0111  ...  ..... ..... 101 ..... 1111011 @i8
+xl_fsh          1101  ...  ..... ..... 101 ..... 1111011 @s8
+xl_fsw          1110  ...  ..... ..... 101 ..... 1111011 @s8
+xl_fsd          1111  ...  ..... ..... 101 ..... 1111011 @s8
 
 xl_lgp_b        00   ................   00 ..... 1011011 @xl_lgp16
 xl_lgp_bu       01   ................   00 ..... 1011011 @xl_lgp16

diff --git a/target/riscv/insn_trans/trans_xxlcz.c.inc b/target/riscv/insn_trans/trans_xxlcz.c.inc
@@ -457,3 +457,122 @@ static bool trans_xl_ffnz(DisasContext *ctx, arg_xl_ffnz *a)
     REQUIRE_XXLCZ(ctx);
     return gen_unary(ctx, a, EXT_NONE, gen_helper_xl_ffnz);
 }
+
+static bool trans_xl_flh(DisasContext *ctx, arg_xl_flh *a)
+{
+    TCGv_i64 dest;
+    TCGv t0;
+
+    REQUIRE_FPU;
+    REQUIRE_ZFHMIN(ctx);
+    REQUIRE_XXLCZ(ctx);
+
+    decode_save_opc(ctx);
+    t0 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+    dest = cpu_fpr[a->rd];
+    tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, MO_TEUW);
+    gen_nanbox_h(dest, dest);
+
+    tcg_gen_addi_tl(t0, t0, a->imm << 1);
+    gen_set_gpr(ctx, a->rs1, t0);
+
+    mark_fs_dirty(ctx);
+    return true;
+}
+
+static bool trans_xl_flw(DisasContext *ctx, arg_xl_flw *a)
+{
+    TCGv_i64 dest;
+    TCGv addr;
+
+    REQUIRE_FPU;
+    REQUIRE_EXT(ctx, RVF);
+    REQUIRE_XXLCZ(ctx);
+
+    decode_save_opc(ctx);
+    addr = get_address(ctx, a->rs1, 0);
+    dest = cpu_fpr[a->rd];
+    tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL);
+    gen_nanbox_s(dest, dest);
+
+    tcg_gen_addi_tl(addr, addr, a->imm << 2);
+    gen_set_gpr(ctx, a->rs1, addr);
+
+    mark_fs_dirty(ctx);
+    return true;
+}
+
+static bool trans_xl_fld(DisasContext *ctx, arg_xl_fld *a)
+{
+    TCGv addr;
+
+    REQUIRE_FPU;
+    REQUIRE_EXT(ctx, RVD);
+    REQUIRE_XXLCZ(ctx);
+
+    decode_save_opc(ctx);
+    addr = get_address(ctx, a->rs1, 0);
+    tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEUQ);
+
+    tcg_gen_addi_tl(addr, addr, a->imm << 3);
+    gen_set_gpr(ctx, a->rs1, addr);
+
+    mark_fs_dirty(ctx);
+    return true;
+}
+
+static bool trans_xl_fsh(DisasContext *ctx, arg_xl_fsh *a)
+{
+    TCGv t0;
+
+    REQUIRE_FPU;
+    REQUIRE_ZFHMIN(ctx);
+    REQUIRE_XXLCZ(ctx);
+
+    decode_save_opc(ctx);
+    t0 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+    tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUW);
+
+    tcg_gen_addi_tl(t0, t0, a->imm << 1);
+    gen_set_gpr(ctx, a->rs1, t0);
+
+    return true;
+}
+
+static bool trans_xl_fsw(DisasContext *ctx, arg_xl_fsw *a)
+{
+    TCGv addr;
+
+    REQUIRE_FPU;
+    REQUIRE_EXT(ctx, RVF);
+    REQUIRE_XXLCZ(ctx);
+
+    decode_save_opc(ctx);
+    addr = get_address(ctx, a->rs1, 0);
+    tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL);
+
+    tcg_gen_addi_tl(addr, addr, a->imm << 2);
+    gen_set_gpr(ctx, a->rs1, addr);
+
+    return true;
+}
+
+static bool trans_xl_fsd(DisasContext *ctx, arg_xl_fsd *a)
+{
+    TCGv addr;
+
+    REQUIRE_FPU;
+    REQUIRE_EXT(ctx, RVD);
+    REQUIRE_XXLCZ(ctx);
+
+    decode_save_opc(ctx);
+    addr = get_address(ctx, a->rs1, a->imm);
+    tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUQ);
+
+    tcg_gen_addi_tl(addr, addr, a->imm << 3);
+    gen_set_gpr(ctx, a->rs1, addr);
+
+    return true;
+}