Tracer : keep pc64 64 targets failed

openhwgroup · Jan 27, 2025 · a8e43e1 · a8e43e1
1 parent 3ae5feb
commit a8e43e1
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Showing 3 changed files with 15 additions and 9 deletions.
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
@@ -171,6 +171,7 @@ smoke-gen:
   script:
     - bash verif/regress/smoke-gen_tests.sh
     - cp verif/sim/seedlist.yaml artifacts/logs/
+    - cp verif/sim/uvm_seed.log artifacts/logs/
     - !reference [.simu_after_script]
 
 smoke-bench:
@@ -452,6 +453,7 @@ generated_tests:
     - source verif/regress/dv-generated-tests.sh
     - mv verif/sim/vcs_results/default/vcs.d/simv.vdb artifacts/coverage
     - mv verif/sim/seedlist.yaml artifacts/coverage
+    - mv verif/sim/uvm_seed.log artifacts/coverage
     - python3 .gitlab-ci/scripts/report_pass.py
 
 .generated_xif_tests:
@@ -472,6 +474,7 @@ generated_tests:
     - source verif/regress/dv-generated-xif-tests.sh
     - mv verif/sim/vcs_results/default/vcs.d/simv.vdb artifacts/coverage
     - mv verif/sim/seedlist.yaml artifacts/coverage
+    - mv verif/sim/uvm_seed.log artifacts/coverage
     - python3 .gitlab-ci/scripts/report_pass.py
 
 directed_isacov-tests:
@@ -491,6 +494,7 @@ directed_isacov-tests:
     - mkdir -p artifacts/coverage
     - source verif/regress/dv-generated-tests.sh
     - mv verif/sim/vcs_results/default/vcs.d/simv.vdb artifacts/coverage
+    - mv verif/sim/uvm_seed.log artifacts/coverage
     - python3 .gitlab-ci/scripts/report_pass.py
 
 csr_embedded_tests:
@@ -507,6 +511,7 @@ csr_embedded_tests:
     - mkdir -p artifacts/coverage
     - source verif/regress/dv-csr-embedded-tests.sh
     - mv verif/sim/vcs_results/default/vcs.d/simv.vdb artifacts/coverage
+    - mv verif/sim/uvm_seed.log artifacts/coverage
     - python3 .gitlab-ci/scripts/report_tandem.py verif/sim/out*/"$DV_SIMULATORS"_sim
 
 .backend_test:
@@ -605,6 +610,7 @@ code_coverage-report:
     - mkdir -p verif/sim/vcs_results/default/vcs.d
     - mv artifacts/coverage/simv.vdb verif/sim/vcs_results/default/vcs.d/
     - mv artifacts/coverage/seedlist.yaml verif/sim/seedlist.yaml
+    - mv artifacts/coverage/uvm_seed.log verif/sim/uvm_seed.log
     - make -C verif/sim generate_cov_dash
     - mv verif/sim/urgReport artifacts/cov_reports/
     - python3 .gitlab-ci/scripts/report_coverage.py artifacts/cov_reports/urgReport/hierarchy.txt artifacts/cov_reports/urgReport/"feature.CVA6 Verification Master Plan1.7.-1268999905.txt"

diff --git a/corev_apu/tb/rvfi_tracer.sv b/corev_apu/tb/rvfi_tracer.sv
@@ -64,7 +64,7 @@ module rvfi_tracer #(
 
   logic [31:0] cycles;
   // Generate the trace based on RVFI
-  logic [CVA6Cfg.XLEN-1:0] pc;
+  logic [63:0] pc64;
   string cause;
   logic[31:0] end_of_test_q;
   logic[31:0] end_of_test_d;
@@ -74,25 +74,25 @@ module rvfi_tracer #(
   always_ff @(posedge clk_i) begin
     end_of_test_q <= (rst_ni && (end_of_test_d[0] == 1'b1)) ? end_of_test_d : 0;
     for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
-      pc = {{CVA6Cfg.XLEN-CVA6Cfg.VLEN{rvfi_i[i].pc_rdata[CVA6Cfg.VLEN-1]}}, rvfi_i[i].pc_rdata};
+      pc64 = {{CVA6Cfg.XLEN-CVA6Cfg.VLEN{rvfi_i[i].pc_rdata[CVA6Cfg.VLEN-1]}}, rvfi_i[i].pc_rdata};
       // print the instruction information if the instruction is valid or a trap is taken
       if (rvfi_i[i].valid) begin
         // Instruction information
         if (rvfi_i[i].intr[2]) begin
            $fwrite(f, "core   INTERRUPT 0: 0x%h (0x%h) DASM(%h)\n",
-             pc, rvfi_i[i].insn, rvfi_i[i].insn);
+             pc64, rvfi_i[i].insn, rvfi_i[i].insn);
         end
         else begin
            $fwrite(f, "core   0: 0x%h (0x%h) DASM(%h)\n",
-             pc, rvfi_i[i].insn, rvfi_i[i].insn);
+             pc64, rvfi_i[i].insn, rvfi_i[i].insn);
         end
         // Destination register information
         if (rvfi_i[i].insn[1:0] != 2'b11) begin
           $fwrite(f, "%h 0x%h (0x%h)",
-            rvfi_i[i].mode, pc, rvfi_i[i].insn[15:0]);
+            rvfi_i[i].mode, pc64, rvfi_i[i].insn[15:0]);
         end else begin
           $fwrite(f, "%h 0x%h (0x%h)",
-            rvfi_i[i].mode, pc, rvfi_i[i].insn);
+            rvfi_i[i].mode, pc64, rvfi_i[i].insn);
         end
         // Decode instruction to know if destination register is FP register.
         // Handle both uncompressed and compressed instructions.
@@ -138,9 +138,9 @@ module rvfi_tracer #(
             32'hb: cause = "ENV_CALL_MMODE";
           endcase;
           if (rvfi_i[i].insn[1:0] != 2'b11) begin
-            $fwrite(f, "%s exception @ 0x%h (0x%h)\n", cause, pc, rvfi_i[i].insn[15:0]);
+            $fwrite(f, "%s exception @ 0x%h (0x%h)\n", cause, pc64, rvfi_i[i].insn[15:0]);
           end else begin
-            $fwrite(f, "%s exception @ 0x%h (0x%h)\n", cause, pc, rvfi_i[i].insn);
+            $fwrite(f, "%s exception @ 0x%h (0x%h)\n", cause, pc64, rvfi_i[i].insn);
           end
         end
       end

diff --git a/verif/sim/cva6.py b/verif/sim/cva6.py
@@ -719,7 +719,7 @@ def parse_args(cwd):
                       help="simulation run options")
   parser.add_argument("--isscomp_opts", type=str, default="",
                       help="simulation comp options")
-  parser.add_argument("--isspostrun_opts", type=str, default="0x80000000",
+  parser.add_argument("--isspostrun_opts", type=str, default="0x0000000080000000",
                       help="simulation post run options")
   parser.add_argument("-s", "--steps", type=str, default="all",
                       help="Run steps: gen,gcc_compile,iss_sim,iss_cmp", dest="steps")