nRF54l15DK board support

boards/nordic/nrf54l15dk/Kconfig.defconfig

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+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_NRF54L15DK_NRF54L15_CPUAPP
+
+config BT_CTLR
+	default BT
+
+config ROM_START_OFFSET
+	default 0x800 if BOOTLOADER_MCUBOOT
+
+endif # BOARD_NRF54L15DK_NRF54L15_CPUAPP

boards/nordic/nrf54l15dk/Kconfig.nrf54l15dk

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+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_NRF54L15DK
+	select SOC_NRF54L15_CPUAPP if BOARD_NRF54L15DK_NRF54L15_CPUAPP
+	select SOC_NRF54L15_CPUFLPR if BOARD_NRF54L15DK_NRF54L15_CPUFLPR || \
+					    BOARD_NRF54L15DK_NRF54L15_CPUFLPR_XIP

boards/nordic/nrf54l15dk/board.cmake

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+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_SOC_NRF54L15_CPUAPP)
+  board_runner_args(jlink "--device=cortex-m33" "--speed=4000")
+elseif(CONFIG_SOC_NRF54L15_CPUFLPR)
+  board_runner_args(jlink "--speed=4000")
+endif()
+
+include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/nordic/nrf54l15dk/board.yml

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+board:
+  name: nrf54l15dk
+  vendor: nordic
+  socs:
+  - name: nrf54l15
+    variants:
+    - name: xip
+      cpucluster: cpuflpr

boards/nordic/nrf54l15dk/doc/index.rst

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+.. _nrf54l15dk_nrf54l15:
+
+nRF54L15 DK
+############
+
+Overview
+********
+
+.. note::
+
+   All software for the nRF54L15 SoC is experimental and hardware availability
+   is restricted to the participants in the limited sampling program.
+
+The nRF54L15 Development Kit hardware provides support for the Nordic Semiconductor
+nRF54L15 Arm Cortex-M33 CPU and the following devices:
+
+* :abbr:`SAADC (Successive Approximation Analog to Digital Converter)`
+* CLOCK
+* RRAM
+* :abbr:`GPIO (General Purpose Input Output)`
+* :abbr:`TWIM (I2C-compatible two-wire interface master with EasyDMA)`
+* :abbr:`MPU (Memory Protection Unit)`
+* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
+* :abbr:`PWM (Pulse Width Modulation)`
+* :abbr:`GRTC (Global real-time counter)`
+* Segger RTT (RTT Console)
+* :abbr:`SPI (Serial Peripheral Interface)`
+* :abbr:`UARTE (Universal asynchronous receiver-transmitter)`
+* :abbr:`WDT (Watchdog Timer)`
+
+.. figure:: img/nrf54l15dk_nrf54l15.webp
+     :align: center
+     :alt: nRF54L15 DK
+
+     nRF54L15 DK (Credit: Nordic Semiconductor)
+
+Hardware
+********
+
+nRF54L15 DK has two crystal oscillators:
+
+* High-frequency 32 MHz crystal oscillator (HFXO)
+* Low-frequency 32.768 kHz crystal oscillator (LFXO)
+
+The crystal oscillators can be configured to use either
+internal or external capacitors.
+
+Supported Features
+==================
+
+The ``nrf54l15dk/nrf54l15/cpuapp`` board target configuration supports the following
+hardware features:
+
++-----------+------------+----------------------+
+| Interface | Controller | Driver/Component     |
++===========+============+======================+
+| CLOCK     | on-chip    | clock_control        |
++-----------+------------+----------------------+
+| GPIO      | on-chip    | gpio                 |
++-----------+------------+----------------------+
+| GRTC      | on-chip    | counter              |
++-----------+------------+----------------------+
+| MPU       | on-chip    | arch/arm             |
++-----------+------------+----------------------+
+| NVIC      | on-chip    | arch/arm             |
++-----------+------------+----------------------+
+| PWM       | on-chip    | pwm                  |
++-----------+------------+----------------------+
+| RRAM      | on-chip    | flash                |
++-----------+------------+----------------------+
+| RTT       | Segger     | console              |
++-----------+------------+----------------------+
+| SAADC     | on-chip    | adc                  |
++-----------+------------+----------------------+
+| SPI(M/S)  | on-chip    | spi                  |
++-----------+------------+----------------------+
+| SPU       | on-chip    | system protection    |
++-----------+------------+----------------------+
+| TWIM      | on-chip    | i2c                  |
++-----------+------------+----------------------+
+| UARTE     | on-chip    | serial               |
++-----------+------------+----------------------+
+| WDT       | on-chip    | watchdog             |
++-----------+------------+----------------------+
+
+Other hardware features have not been enabled yet for this board.
+
+Programming and Debugging
+*************************
+
+Applications for the ``nrf54l15dk/nrf54l15/cpuapp`` board target can be
+built, flashed, and debugged in the usual way. See
+:ref:`build_an_application` and :ref:`application_run` for more details on
+building and running.
+
+Applications for the ``nrf54l15dk/nrf54l15/cpuflpr`` board target need
+to be build as multicore configuration with code snippet called ``vpr_launcher``
+for the application core.
+
+Enter the following command to compile ``hello_world`` for the FLPR core::
+ west build -p -b nrf54l15pdk/nrf54l15/cpuflpr --sysbuild -- -DSB_VPR_LAUNCHER=y
+
+Flashing
+========
+
+As an example, this section shows how to build and flash the :ref:`hello_world`
+application.
+
+.. warning::
+
+   When programming the device, you might get an error similar to the following message::
+
+    ERROR: The operation attempted is unavailable due to readback protection in
+    ERROR: your device. Please use --recover to unlock the device.
+
+   This error occurs when readback protection is enabled.
+   To disable the readback protection, you must *recover* your device.
+
+   Enter the following command to recover the core::
+
+    west flash --recover
+
+   The ``--recover`` command erases the flash memory and then writes a small binary into
+   the recovered flash memory.
+   This binary prevents the readback protection from enabling itself again after a pin
+   reset or power cycle.
+
+Follow the instructions in the :ref:`nordic_segger` page to install
+and configure all the necessary software. Further information can be
+found in :ref:`nordic_segger_flashing`.
+
+To build and program the sample to the nRF54L15 DK, complete the following steps:
+
+First, connect the nRF54L15 DK to you computer using the IMCU USB port on the DK.
+Next, build the sample by running the following command:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: nrf54l15dk/nrf54l15/cpuapp
+   :goals: build flash
+
+Testing the LEDs and buttons in the nRF54L15 DK
+************************************************
+
+Test the nRF54L15 DK with a :zephyr:code-sample:`blinky` sample.

boards/nordic/nrf54l15dk/nrf54l15_cpuapp_common.dtsi

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+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* This file is common to the secure and non-secure domain */
+
+#include <nordic/nrf54l15_cpuapp.dtsi>
+#include "nrf54l15dk_nrf54l15-common.dtsi"
+
+/ {
+	chosen {
+		zephyr,console = &uart20;
+		zephyr,shell-uart = &uart20;
+		zephyr,uart-mcumgr = &uart20;
+		zephyr,bt-mon-uart = &uart20;
+		zephyr,bt-c2h-uart = &uart20;
+		zephyr,flash-controller = &rram_controller;
+		zephyr,flash = &cpuapp_rram;
+		zephyr,ieee802154 = &ieee802154;
+	};
+};
+
+&cpuapp_sram {
+	status = "okay";
+};
+
+&lfxo {
+	load-capacitors = "internal";
+	load-capacitance-femtofarad = <15500>;
+};
+
+&hfxo {
+	load-capacitors = "internal";
+	load-capacitance-femtofarad = <15000>;
+};
+
+&regulators {
+	status = "okay";
+};
+
+&vregmain {
+	status = "okay";
+	regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
+};
+
+&grtc {
+	owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;
+	/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
+	child-owned-channels = <3 4 7 8 9 10 11>;
+	status = "okay";
+};
+
+&cpuapp_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x0 DT_SIZE_K(64)>;
+		};
+		slot0_partition: partition@10000 {
+			label = "image-0";
+			reg = <0x10000 DT_SIZE_K(324)>;
+		};
+		slot0_ns_partition: partition@61000 {
+			label = "image-0-nonsecure";
+			reg = <0x61000 DT_SIZE_K(324)>;
+		};
+		slot1_partition: partition@b2000 {
+			label = "image-1";
+			reg = <0xb2000 DT_SIZE_K(324)>;
+		};
+		slot1_ns_partition: partition@103000 {
+			label = "image-1-nonsecure";
+			reg = <0x103000 DT_SIZE_K(324)>;
+		};
+		/* 32k from 0x154000 to 0x15bfff reserved for TF-M partitions */
+		storage_partition: partition@15c000 {
+			label = "storage";
+			reg = <0x15c000 DT_SIZE_K(36)>;
+		};
+	};
+};
+
+&uart20 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpiote20 {
+	status = "okay";
+};
+
+&gpiote30 {
+	status = "okay";
+};
+
+&radio {
+	status = "okay";
+};
+
+&ieee802154 {
+	status = "okay";
+};
+
+&temp {
+	status = "okay";
+};
+
+&clock {
+	status = "okay";
+};
+
+&spi00 {
+	status = "okay";
+	cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&spi00_default>;
+	pinctrl-1 = <&spi00_sleep>;
+	pinctrl-names = "default", "sleep";
+
+	mx25r64: mx25r6435f@0 {
+		compatible = "jedec,spi-nor";
+		status = "okay";
+		reg = <0>;
+		spi-max-frequency = <8000000>;
+		jedec-id = [c2 28 17];
+		sfdp-bfp = [
+			e5 20 f1 ff  ff ff ff 03  44 eb 08 6b  08 3b 04 bb
+			ee ff ff ff  ff ff 00 ff  ff ff 00 ff  0c 20 0f 52
+			10 d8 00 ff  23 72 f5 00  82 ed 04 cc  44 83 48 44
+			30 b0 30 b0  f7 c4 d5 5c  00 be 29 ff  f0 d0 ff ff
+		];
+		size = <67108864>;
+		has-dpd;
+		t-enter-dpd = <10000>;
+		t-exit-dpd = <35000>;
+	};
+};
+
+&adc {
+	status = "okay";
+};