Process completed with exit code 1.

See https://docs.zephyrproject.org/latest/contribute/guidelines.html#clang-format for more details. You may want to run clang-format on this change: -#define PAD_PD(inst) \ - .pad_pd = DT_INST_PHA_BY_NAME_OR(inst, power_domains, pad, id, \ - NRF_GPD_SLOW_MAIN), +#define PAD_PD(inst) \ + .pad_pd = DT_INST_PHA_BY_NAME_OR(inst, power_domains, pad, id, NRF_GPD_SLOW_MAIN), #else #define PAD_PD(inst) #endif -#define GPIO_NRF_DEVICE(id) \ - GPIOTE_CHECK(id); \ - static const struct gpio_nrfx_cfg gpio_nrfx_p##id##_cfg = { \ - .common = { \ - .port_pin_mask = \ - GPIO_PORT_PIN_MASK_FROM_DT_INST(id), \ - }, \ - .port = _CONCAT(NRF_P, DT_INST_PROP(id, port)), \ - .port_num = DT_INST_PROP(id, port), \ - .edge_sense = DT_INST_PROP_OR(id, sense_edge_mask, 0), \ - .gpiote = GPIOTE_INSTANCE(id), \ - PAD_PD(id) \ - }; \ - \ - static struct gpio_nrfx_data gpio_nrfx_p##id##_data; \ - \ - DEVICE_DT_INST_DEFINE(id, gpio_nrfx_init, \ - NULL, \ - &gpio_nrfx_p##id##_data, \ - &gpio_nrfx_p##id##_cfg, \ - PRE_KERNEL_1, \ - CONFIG_GPIO_INIT_PRIORITY, \ - &gpio_nrfx_drv_api_funcs); +#define GPIO_NRF_DEVICE(id) \ + GPIOTE_CHECK(id); \ + static const struct gpio_nrfx_cfg gpio_nrfx_p##id##_cfg = { \ + .common = \ + { \ + .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(id), \ + }, \ + .port = _CONCAT(NRF_P, DT_INST_PROP(id, port)), \ + .port_num = DT_INST_PROP(id, port), \ + .edge_sense = DT_INST_PROP_OR(id, sense_edge_mask, 0), \ + .gpiote = GPIOTE_INSTANCE(id), \ + PAD_PD(id)}; \ + \ + static struct gpio_nrfx_data gpio_nrfx_p##id##_data; \ + \ + DEVICE_DT_INST_DEFINE(id, gpio_nrfx_init, NULL, &gpio_nrfx_p##id##_data, \ + &gpio_nrfx_p##id##_cfg, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \ + &gpio_nrfx_drv_api_funcs); File:drivers/gpio/gpio_nrfx.c Line:575 You may want to run clang-format on this change: -#define NRF_FUN_POS 24U +#define NRF_FUN_POS 24U /** Mask for the function field. */ -#define NRF_FUN_MSK 0xFFU +#define NRF_FUN_MSK 0xFFU File:include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h Line:33 You may want to run clang-format on this change: - #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_POWER_NORDIC_NRF_GLOBAL_PD #define ZEPHYR_INCLUDE_DT_BINDINGS_POWER_NORDIC_NRF_GLOBAL_PD /* numbers aligned to nrfs service identifiers */ -#define NRF_GPD_SLOW_MAIN 2U -#define NRF_GPD_SLOW_ACTIVE 1U -#define NRF_GPD_FAST_MAIN 3U +#define NRF_GPD_SLOW_MAIN 2U +#define NRF_GPD_SLOW_ACTIVE 1U +#define NRF_GPD_FAST_MAIN 3U File:include/zephyr/dt-bindings/power/nordic-nrf-gpd.h Line:14 You may want to run clang-format on this change: -#define Z_PM_DEVICE_POWER_DOMAIN_INIT(_node_id) \ - .domain = DEVICE_DT_GET_OR_NULL(DT_PHANDLE(_node_id, \ - power_domains)), +#define Z_PM_DEVICE_POWER_DOMAIN_INIT(_node_id) \ + .domain = DEVICE_DT_GET_OR_NULL(DT_PHANDLE(_node_id, power_domains)), File:include/zephyr/pm/device.h Line:212 You may want to run clang-format on this c

drivers/gpio/gpio_nrfx.c:575 -#define PAD_PD(inst) \ - .pad_pd = DT_INST_PHA_BY_NAME_OR(inst, power_domains, pad, id, \ - NRF_GPD_SLOW_MAIN), +#define PAD_PD(inst) \ + .pad_pd = DT_INST_PHA_BY_NAME_OR(inst, power_domains, pad, id, NRF_GPD_SLOW_MAIN), #else #define PAD_PD(inst) #endif -#define GPIO_NRF_DEVICE(id) \ - GPIOTE_CHECK(id); \ - static const struct gpio_nrfx_cfg gpio_nrfx_p##id##_cfg = { \ - .common = { \ - .port_pin_mask = \ - GPIO_PORT_PIN_MASK_FROM_DT_INST(id), \ - }, \ - .port = _CONCAT(NRF_P, DT_INST_PROP(id, port)), \ - .port_num = DT_INST_PROP(id, port), \ - .edge_sense = DT_INST_PROP_OR(id, sense_edge_mask, 0), \ - .gpiote = GPIOTE_INSTANCE(id), \ - PAD_PD(id) \ - }; \ - \ - static struct gpio_nrfx_data gpio_nrfx_p##id##_data; \ - \ - DEVICE_DT_INST_DEFINE(id, gpio_nrfx_init, \ - NULL, \ - &gpio_nrfx_p##id##_data, \ - &gpio_nrfx_p##id##_cfg, \ - PRE_KERNEL_1, \ - CONFIG_GPIO_INIT_PRIORITY, \ - &gpio_nrfx_drv_api_funcs); +#define GPIO_NRF_DEVICE(id) \ + GPIOTE_CHECK(id); \ + static const struct gpio_nrfx_cfg gpio_nrfx_p##id##_cfg = { \ + .common = \ + { \ + .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(id), \ + }, \ + .port = _CONCAT(NRF_P, DT_INST_PROP(id, port)), \ + .port_num = DT_INST_PROP(id, port), \ + .edge_sense = DT_INST_PROP_OR(id, sense_edge_mask, 0), \ + .gpiote = GPIOTE_INSTANCE(id), \ + PAD_PD(id)}; \ + \ + static struct gpio_nrfx_data gpio_nrfx_p##id##_data; \ + \ + DEVICE_DT_INST_DEFINE(id, gpio_nrfx_init, NULL, &gpio_nrfx_p##id##_data, \ + &gpio_nrfx_p##id##_cfg, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \ + &gpio_nrfx_drv_api_funcs);

include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h:33 -#define NRF_FUN_POS 24U +#define NRF_FUN_POS 24U /** Mask for the function field. */ -#define NRF_FUN_MSK 0xFFU +#define NRF_FUN_MSK 0xFFU

include/zephyr/dt-bindings/power/nordic-nrf-gpd.h:14 - #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_POWER_NORDIC_NRF_GLOBAL_PD #define ZEPHYR_INCLUDE_DT_BINDINGS_POWER_NORDIC_NRF_GLOBAL_PD /* numbers aligned to nrfs service identifiers */ -#define NRF_GPD_SLOW_MAIN 2U -#define NRF_GPD_SLOW_ACTIVE 1U -#define NRF_GPD_FAST_MAIN 3U +#define NRF_GPD_SLOW_MAIN 2U +#define NRF_GPD_SLOW_ACTIVE 1U +#define NRF_GPD_FAST_MAIN 3U

include/zephyr/pm/device.h:212 -#define Z_PM_DEVICE_POWER_DOMAIN_INIT(_node_id) \ - .domain = DEVICE_DT_GET_OR_NULL(DT_PHANDLE(_node_id, \ - power_domains)), +#define Z_PM_DEVICE_POWER_DOMAIN_INIT(_node_id) \ + .domain = DEVICE_DT_GET_OR_NULL(DT_PHANDLE(_node_id, power_domains)),

soc/intel/intel_adsp/ace/include/ace30/adsp_boot.h:10 -#define DSPCS_REG 0x178d00 +#define DSPCS_REG 0x178d00

soc/intel/intel_adsp/ace/include/ace30/adsp_boot.h:61 -#define DSPCS_CTL_SPA BIT(0) -#define DSPCS_CTL_CPA BIT(8) +#define DSPCS_CTL_SPA BIT(0) +#define DSPCS_CTL_CPA BIT(8) -#define DSPBR_BCTL_BYPROM BIT(0) -#define DSPBR_BCTL_WAITIPCG BIT(16) -#define DSPBR_BCTL_WAITIPPG BIT(17) +#define DSPBR_BCTL_BYPROM BIT(0) +#define DSPBR_BCTL_WAITIPCG BIT(16) +#define DSPBR_BCTL_WAITIPPG BIT(17) -#define DSPBR_BATTR_LPSCTL_RESTORE_BOOT BIT(12) -#define DSPBR_BATTR_LPSCTL_HP_CLOCK_BOOT BIT(13) -#define DSPBR_BATTR_LPSCTL_LP_CLOCK_BOOT BIT(14) -#define DSPBR_BATTR_LPSCTL_L1_MIN_WAY BIT(15) -#define DSPBR_BATTR_LPSCTL_BATTR_SLAVE_CORE BIT(16) +#define DSPBR_BATTR_LPSCTL_RESTORE_BOOT BIT(12) +#define DSPBR_BATTR_LPSCTL_HP_CLOCK_BOOT BIT(13) +#define DSPBR_BATTR_LPSCTL_LP_CLOCK_BOOT BIT(14) +#define DSPBR_BATTR_LPSCTL_L1_MIN_WAY BIT(15) +#define DSPBR_BATTR_LPSCTL_BATTR_SLAVE_CORE BIT(16) -#define DSPBR_WDT_RESUME BIT(8) -#define DSPBR_WDT_RESTART_COMMAND 0x76 +#define DSPBR_WDT_RESUME BIT(8) +#define DSPBR_WDT_RESTART_COMMAND 0x76

soc/intel/intel_adsp/ace/include/ace30/adsp_interrupt.h:39 -#define ACE_INTL_HIPC 0 -#define ACE_INTL_SBIPC 1 -#define ACE_INTL_ML 2 -#define ACE_INTL_IDCA 3 -#define ACE_INTL_LPVML 4 -#define ACE_INTL_SHA 5 -#define ACE_INTL_L1L2M 6 -#define ACE_INTL_I2S 7 -#define ACE_INTL_DMIC 8 -#define ACE_INTL_SNDW 9 -#define ACE_INTL_TTS 10 -#define ACE_INTL_WDT 11 +#define ACE_INTL_HIPC 0 +#define ACE_INTL_SBIPC 1 +#define ACE_INTL_ML 2 +#define ACE_INTL_IDCA 3 +#define ACE_INTL_LPVML 4 +#define ACE_INTL_SHA 5 +#define ACE_INTL_L1L2M 6 +#define ACE_INTL_I2S 7 +#define ACE_INTL_DMIC 8 +#define ACE_INTL_SNDW 9 +#define ACE_INTL_TTS 10 +#define ACE_INTL_WDT 11 #define ACE_INTL_HDAHIDMA 12 #define ACE_INTL_HDAHODMA 13 #define ACE_INTL_HDALIDMA 14 #define ACE_INTL_HDALODMA 15 -#define ACE_INTL_I3C 16 -#define ACE_INTL_GPDMA 17 -#define ACE_INTL_PWM 18 -#define ACE_INTL_I2C 19 -#define ACE_INTL_SPI 20 -#define ACE_INTL_UART 21 -#define ACE_INTL_GPIO 22 -#define ACE_INTL_UAOL 23 -#define ACE_INTL_IDCB 24 -#define ACE_INTL_DCW 25 -#define ACE_INTL_DTF 26 -#define ACE_INTL_FLV 27 -#define ACE_INTL_DPDMA 28 +#define ACE_INTL_I3C 16 +#define ACE_INTL_GPDMA 17 +#define ACE_INTL_PWM 18 +#define ACE_INTL_I2C 19 +#define ACE_INTL_SPI 20 +#define ACE_INTL_UART 21 +#define ACE_INTL_GPIO 22 +#define ACE_INTL_UAOL 23 +#define ACE_INTL_IDCB 24 +#define ACE_INTL_DCW 25 +#define ACE_INTL_DTF 26 +#define ACE_INTL_FLV 27 +#define ACE_INTL_DPDMA 28

soc/intel/intel_adsp/ace/include/ace30/adsp_interrupt.h:82 -#define ACE_DINT ((volatile struct ace_dint *)DXHIPCIE_REG) +#define ACE_DINT ((volatile struct ace_dint *)DXHIPCIE_REG) #define XTENSA_IRQ_NUM_MASK 0xff #define XTENSA_IRQ_NUM_SHIFT 0 -#define XTENSA_IRQ_NUMBER(_irq) ((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK) +#define XTENSA_IRQ_NUMBER(_irq) ((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK) /* Convert between IRQ_CONNECT() numbers and ACE_INTL_* interrupts */ -#define ACE_IRQ_NUM_SHIFT 8 -#define ACE_IRQ_NUM_MASK 0xFFU +#define ACE_IRQ_NUM_SHIFT 8 +#define ACE_IRQ_NUM_MASK 0xFFU

soc/intel/intel_adsp/ace/include/ace30/adsp_ipc_regs.h:49 -#define INTEL_ADSP_IPC_BUSY BIT(31) -#define INTEL_ADSP_IPC_DONE BIT(31) +#define INTEL_ADSP_IPC_BUSY BIT(31) +#define INTEL_ADSP_IPC_DONE BIT(31)