Introduce nRF7120 SoC and board definitions to sdk-nrf

boards/nordic/nrf7120pdk/Kconfig

@@ -0,0 +1,34 @@
+# nRF7120 PDK board configuration
+
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+
+if BOARD_NRF7120PDK_NRF7120_ENGA_CPUAPP_NS
+
+config NRF_MPC_REGION_SIZE
+	hex
+	default 0x1000
+	help
+	  Region size for the Memory Protection Controller (MPC) in bytes.
+
+config NRF_TRUSTZONE_FLASH_REGION_SIZE
+	hex
+	default NRF_MPC_REGION_SIZE
+	help
+	  This defines the flash region size from the TRUSTZONE perspective.
+	  It is used when configuring the TRUSTZONE and when setting alignments
+	  requirements for the partitions.
+	  This abstraction allows us to configure TRUSTZONE without depending
+	  on peripheral specific symbols.
+
+config NRF_TRUSTZONE_RAM_REGION_SIZE
+	hex
+	default NRF_MPC_REGION_SIZE
+	help
+	  This defines the RAM region size from the TRUSTZONE perspective.
+	  It is used when configuring the TRUSTZONE and when setting alignments
+	  requirements for the partitions.
+	  This abstraction allows us to configure TRUSTZONE without depending
+	  on peripheral specific symbols.
+
+endif # BOARD_NRF7120PDK_NRF7120_ENGA_CPUAPP_NS

boards/nordic/nrf7120pdk/Kconfig.defconfig

@@ -0,0 +1,37 @@
+
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+if BOARD_NRF7120PDK_NRF7120_ENGA_CPUAPP
+config BT_CTLR
+	default BT
+
+config ROM_START_OFFSET
+	default 0 if PARTITION_MANAGER_ENABLED
+	default 0x800 if BOOTLOADER_MCUBOOT
+
+endif # BOARD_NRF7120PDK_NRF7120_ENGA_CPUAPP
+
+if BOARD_NRF7120PDK_NRF7120_ENGA_CPUAPP_NS
+
+config BT_CTLR
+	default BT
+
+# By default, if we build for a Non-Secure version of the board,
+# enable building with TF-M as the Secure Execution Environment.
+config BUILD_WITH_TFM
+	default y
+
+# By default, if we build with TF-M, instruct build system to
+# flash the combined TF-M (Secure) & Zephyr (Non Secure) image
+config TFM_FLASH_MERGED_BINARY
+	default y
+	depends on BUILD_WITH_TFM
+
+endif # BOARD_NRF7120PDK_NRF7120_ENGA_CPUAPP_NS
+
+if BOARD_NRF7120PDK_NRF7120_ENGA_CPUFLPR || BOARD_NRF7120PDK_NRF7120_ENGA_CPUFLPR_XIP
+
+# As FLPR has limited memory most of tests does not fit with asserts enabled.
+config ASSERT
+	default n if ZTEST
+endif # BOARD_NRF7120PDK_NRF7120_ENGA_CPUFLPR || BOARD_NRF7120PDK_NRF7120_ENGA_CPUFLPR_XIP

boards/nordic/nrf7120pdk/Kconfig.nrf7120pdk

@@ -0,0 +1,7 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+config BOARD_NRF7120PDK
+	select SOC_NRF7120_ENGA_CPUAPP if BOARD_NRF7120PDK_NRF7120_ENGA_CPUAPP  || \
+						BOARD_NRF7120PDK_NRF7120_ENGA_CPUAPP_NS
+	select SOC_NRF7120_ENGA_CPUFLPR if BOARD_NRF7120PDK_NRF7120_ENGA_CPUFLPR || \
+					    BOARD_NRF7120PDK_NRF7120_ENGA_CPUFLPR_XIP

boards/nordic/nrf7120pdk/board.cmake

@@ -0,0 +1,20 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+
+if(CONFIG_SOC_NRF7120_ENGA_CPUAPP)
+  board_runner_args(jlink "--device=cortex-m33" "--speed=4000")
+elseif(CONFIG_SOC_NRF7120_ENGA_CPUFLPR)
+  board_runner_args(jlink "--speed=4000")
+endif()
+
+if(BOARD_NRF7120PDK_NRF7120_CPUAPP_NS)
+  set(TFM_PUBLIC_KEY_FORMAT "full")
+endif()
+
+if(CONFIG_TFM_FLASH_MERGED_BINARY)
+  set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex)
+endif()
+
+include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/nordic/nrf7120pdk/board.yml

@@ -0,0 +1,15 @@
+board:
+  name: nrf7120pdk
+  vendor: nordic
+  socs:
+  - name: nrf7120_enga
+    variants:
+    - name: xip
+      cpucluster: cpuflpr
+    - name: ns
+      cpucluster: cpuapp
+  revision:
+    format: major.minor.patch
+    default: "0.0.0"
+    revisions:
+    - name: "0.0.0"

boards/nordic/nrf7120pdk/nrf7120_enga_cpuapp_common.dtsi

@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+/* This file is common to the secure and non-secure domain */
+
+#include "arm/nordic/nrf7120_enga_cpuapp.dtsi"
+#include "nrf7120pdk_nrf7120_enga-common.dtsi"
+
+/ {
+	chosen {
+		zephyr,console = &uart20;
+		zephyr,shell-uart = &uart20;
+		zephyr,uart-mcumgr = &uart20;
+		zephyr,flash = &cpuapp_mram;
+		zephyr,ieee802154 = &ieee802154;
+	};
+};
+
+&cpuapp_sram {
+	status = "okay";
+};
+
+&grtc {
+	owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
+	/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
+	child-owned-channels = <3 4 7 8 9 10 11>;
+	status = "okay";
+};
+
+&cpuapp_mram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x0 DT_SIZE_K(64)>;
+		};
+
+		slot0_partition: partition@10000 {
+			label = "image-0";
+			reg = <0x10000 DT_SIZE_K(960)>;
+		};
+
+		slot0_ns_partition: partition@100000 {
+			label = "image-0-nonsecure";
+			reg = <0x100000 DT_SIZE_K(960)>;
+		};
+
+		slot1_partition: partition@1f0000 {
+			label = "image-1";
+			reg = <0x1f0000 DT_SIZE_K(960)>;
+		};
+
+		slot1_ns_partition: partition@2e0000 {
+			label = "image-1-nonsecure";
+			reg = <0x2e0000 DT_SIZE_K(960)>;
+		};
+
+		/* 32k from 0x3d0000 to 0x2d7fff reserved for TF-M partitions */
+		storage_partition: partition@3d8000 {
+			label = "storage";
+			reg = < 0x3d8000 DT_SIZE_K(36)>;
+		};
+	};
+};
+
+&uart20 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpiote20 {
+	status = "okay";
+};
+
+&gpiote30 {
+	status = "okay";
+};
+
+&radio {
+	status = "okay";
+};
+
+&ieee802154 {
+	status = "okay";
+};
+
+&temp {
+	status = "okay";
+};
+
+&clock {
+	status = "okay";
+};
+
+&spi00 {
+	status = "okay";
+	cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&spi00_default>;
+	pinctrl-1 = <&spi00_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&adc {
+	status = "okay";
+};

boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga-common.dtsi

@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+#include "nrf7120pdk_nrf7120_enga-pinctrl.dtsi"
+
+/ {
+	leds {
+		compatible = "gpio-leds";
+		led0: led_0 {
+			gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 0";
+		};
+		led1: led_1 {
+			gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 1";
+		};
+		led2: led_2 {
+			gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 2";
+		};
+		led3: led_3 {
+			gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 3";
+		};
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+		/*
+		 * PWM signal can be exposed on GPIO pin only within same domain.
+		 * There is only one domain which contains both PWM and GPIO:
+		 * PWM20/21/22 and GPIO Port P1.
+		 * Only LEDs connected to P1 can work with PWM, for example LED1.
+		 */
+		pwm_led1: pwm_led_1 {
+			pwms = <&pwm20 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+		button0: button_0 {
+			gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 0";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+		button1: button_1 {
+			gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 1";
+			zephyr,code = <INPUT_KEY_1>;
+		};
+		button2: button_2 {
+			gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 2";
+			zephyr,code = <INPUT_KEY_2>;
+		};
+		button3: button_3 {
+			gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 3";
+			zephyr,code = <INPUT_KEY_3>;
+		};
+	};
+
+	aliases {
+		led0 = &led0;
+		led1 = &led1;
+		led2 = &led2;
+		led3 = &led3;
+		pwm-led0 = &pwm_led1;
+		sw0 = &button0;
+		sw1 = &button1;
+		sw2 = &button2;
+		sw3 = &button3;
+		watchdog0 = &wdt31;
+	};
+};
+
+&uart20 {
+	current-speed = <115200>;
+	pinctrl-0 = <&uart20_default>;
+	pinctrl-1 = <&uart20_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&uart30 {
+	current-speed = <115200>;
+	pinctrl-0 = <&uart30_default>;
+	pinctrl-1 = <&uart30_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&pwm20 {
+	status = "okay";
+	pinctrl-0 = <&pwm20_default>;
+	pinctrl-1 = <&pwm20_sleep>;
+	pinctrl-names = "default", "sleep";
+};