Skip to content

Commit

Permalink
fixes for full column, review comment addressing
Browse files Browse the repository at this point in the history
  • Loading branch information
newling committed Oct 8, 2024
1 parent 3784918 commit f51056d
Show file tree
Hide file tree
Showing 4 changed files with 4 additions and 10 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -7,11 +7,8 @@
#include "iree-amd-aie/IR/AMDAIEAttrs.h"
#include "iree-amd-aie/Transforms/Passes.h"
#include "iree/compiler/Codegen/Dialect/Codegen/IR/IREECodegenAttrs.h"
#include "mlir/Dialect/Linalg/IR/LinalgInterfaces.h"
#include "mlir/Dialect/Linalg/Transforms/Transforms.h"
#include "mlir/Dialect/Tensor/IR/Tensor.h"
#include "mlir/Dialect/Utils/StaticValueUtils.h"
#include "mlir/IR/Diagnostics.h"
#include "mlir/Pass/Pass.h"

#define DEBUG_TYPE "iree-amdaie-pack-and-transpose"
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -574,7 +574,7 @@ static LogicalResult setRootConfigForConvDecomposePipeline(
// Target one column of 4 cores, each core processing a different
// output image row. TODO(newling) use 4x4 array.
// https://github.com/nod-ai/iree-amd-aie/issues/821
tileSizeLevel0 = {1, 4 * OH_1, OW_0, OC_0, 0, 0};
tileSizeLevel0 = {1, 4 * OH_1, OW_0, OC_1, 0, 0};
tileSizeLevel1 = {1, OH_1, OW_0, OC_1, 0, 0};
tileSizeLevel2 = {0, 0, 0, 0, 1, 1, 0};
}
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -6,8 +6,6 @@

#include "iree-amd-aie/Transforms/Passes.h"

#include <memory>

#include "aie/Passes.h"
#include "aievec/Passes.h"
#include "air/Conversion/AIRLoweringPass.h"
Expand Down Expand Up @@ -36,7 +34,6 @@
#include "mlir/Dialect/Affine/Passes.h"
#include "mlir/Dialect/Func/IR/FuncOps.h"
#include "mlir/Dialect/Linalg/Passes.h"
#include "mlir/Dialect/MemRef/IR/MemRef.h"
#include "mlir/Dialect/MemRef/Transforms/Passes.h"
#include "mlir/Pass/PassManager.h"
#include "mlir/Transforms/Passes.h"
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@



// CHECK{LITERAL}: #config = #iree_codegen.lowering_config<tile_sizes = [[1, 1, 4, 4, 0, 0, 0], [1, 1, 4, 4, 0, 0, 0], [0, 0, 0, 0, 1, 1, 1, 0, 0]]>
// CHECK{LITERAL}: #config = #iree_codegen.lowering_config<tile_sizes = [[1, 4, 4, 4, 0, 0, 0], [1, 1, 4, 4, 0, 0, 0], [0, 0, 0, 0, 1, 1, 1, 0, 0]]>
// CHECK{LITERAL}: #packingConfig = #amdaie.packing_config<packing_config = [{packedSizes = [0, 0, 0, 4, 0, 0, 8], transposePackIndices = [0, 1, 2], unpackEmpty = [false, false, true], innerPerm = [[], [1, 0], []], outerPerm = [[0, 1, 3, 2], [], [0, 1, 2, 3]]}]>
#pipeline_layout = #hal.pipeline.layout<bindings = [
<storage_buffer>,
Expand All @@ -29,7 +29,7 @@ func.func @conv_static_dispatch_0_conv_2d_nhwc_hwcf_2x12x12x64x3x3x32_bf16xbf16x

// -----

// CHECK{LITERAL}: #config = #iree_codegen.lowering_config<tile_sizes = [[1, 1, 4, 4, 0, 0], [1, 1, 4, 4, 0, 0], [0, 0, 0, 0, 1, 1, 0]]>
// CHECK{LITERAL}: #config = #iree_codegen.lowering_config<tile_sizes = [[1, 4, 4, 4, 0, 0], [1, 1, 4, 4, 0, 0], [0, 0, 0, 0, 1, 1, 0]]>
// CHECK{LITERAL}: #packingConfig = #amdaie.packing_config<packing_config = [{packedSizes = [0, 0, 0, 4, 0, 0], transposePackIndices = [0, 1, 2], unpackEmpty = [false, false, true], innerPerm = [[], [], []], outerPerm = [[0, 1, 2, 3], [0, 1, 2], [0, 1, 2, 3]]}]>
#pipeline_layout = #hal.pipeline.layout<bindings = [
<storage_buffer>,
Expand Down Expand Up @@ -57,7 +57,7 @@ func.func @conv_depthwise_channel_last_bf16(){
// -----
// Same test as above, but where the operand type is i8. In this case we expect OC tile size 8 (not 4) at level 1. This is because of the instruction size of AIE.

// CHECK{LITERAL}: #config = #iree_codegen.lowering_config<tile_sizes = [[1, 1, 4, 8, 0, 0], [1, 1, 4, 8, 0, 0], [0, 0, 0, 0, 1, 1, 0]]>
// CHECK{LITERAL}: #config = #iree_codegen.lowering_config<tile_sizes = [[1, 4, 4, 8, 0, 0], [1, 1, 4, 8, 0, 0], [0, 0, 0, 0, 1, 1, 0]]>
// CHECK{LITERAL}: #packingConfig = #amdaie.packing_config<packing_config = [{packedSizes = [0, 0, 0, 8, 0, 0], transposePackIndices = [0, 1, 2], unpackEmpty = [false, false, true], innerPerm = [[], [], []], outerPerm = [[0, 1, 2, 3], [0, 1, 2], [0, 1, 2, 3]]}]>
#pipeline_layout = #hal.pipeline.layout<bindings = [
<storage_buffer>,
Expand Down

0 comments on commit f51056d

Please sign in to comment.