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Implement PSL prev() built-in function
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,2 @@ | ||
5ns+1: PSL assertion failed | ||
7ns+1: PSL assertion failed |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,42 @@ | ||
entity psl18 is | ||
end entity; | ||
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library ieee; | ||
use ieee.std_logic_1164.all; | ||
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architecture test of psl18 is | ||
signal clk : std_logic := '0'; | ||
signal i : integer := 0; | ||
signal x : bit_vector(1 to 3) := "101"; | ||
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default clock is rising_edge(clk); | ||
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procedure pulse (signal clk : out std_logic) is | ||
begin | ||
wait for 1 ns; | ||
clk <= '1'; | ||
wait for 1 ns; | ||
clk <= '0'; | ||
end procedure; | ||
begin | ||
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one: assert always i = prev(i) + 1; -- Fails at 7ns | ||
two: assert always x = not prev(x); -- Fails at 5ns | ||
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stim: process is | ||
begin | ||
i <= i + 1; | ||
x <= not x; | ||
pulse(clk); | ||
x <= not x; | ||
i <= i + 1; | ||
pulse(clk); | ||
i <= i + 1; | ||
pulse(clk); -- Error | ||
x <= not x; | ||
pulse(clk); -- Error | ||
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wait; | ||
end process; | ||
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end architecture; |
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Original file line number | Diff line number | Diff line change |
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@@ -1094,3 +1094,4 @@ issue1117 normal,psl,2008 | |
issue1125 normal,2008 | ||
issue1137 normal | ||
tcl3 tcl,fail,gold | ||
psl18 fail,gold,2008 |