Finish moving over to new binary file sys

software/chipwhisperer/capture/scopes/OpenADC.py

@@ -144,16 +144,7 @@ def __init__(self):
     def _getFWPy(self):
         from ...hardware.firmware.open_fw import fwver
         cw_type = self._getCWType()
-        fwver = fwver(cw_type)
-        # if cw_type == "cwlite":
-        #     from ...hardware.firmware.cwlite import fwver
-        # elif cw_type == "cw1200":
-        #     from ...hardware.firmware.cw1200 import fwver # type: ignore
-        # elif cw_type in ["cwhusky", "cwhuskyplus"]:
-        #     from ...hardware.firmware.cwhusky import fwver # type: ignore
-        # else:
-        #     raise ValueError('Unknown cw_type: %s' % cw_type)
-        return fwver
+        return fwver(cw_type)
 
     def reload_fpga(self, bitstream=None, reconnect=True, prog_speed=1E6):
         """(Re)loads a FPGA bitstream (even if already configured).

software/chipwhisperer/capture/targets/CW305.py

@@ -121,8 +121,8 @@ class CW305(TargetTemplate, ChipWhispererCommonInterface):
 
 
     def _getFWPy(self):
-        from ...hardware.firmware.cw305 import fwver
-        return fwver
+        from ...hardware.firmware.open_fw import fwver
+        return fwver("cw305")
 
     def __init__(self):
         import chipwhisperer as cw
@@ -477,7 +477,8 @@ def _con(self, scope=None, bsfile=None, force=False, fpga_id=None, defines_files
             if self.fpga.isFPGAProgrammed() == False or force:
                 if bsfile is None:
                     if not fpga_id is None:
-                        from chipwhisperer.hardware.firmware.cw305 import getsome
+                        from ...hardware.firmware.open_fw import getsome_generator
+                        getsome = getsome_generator("cw305")
                         if self.target_name == 'AES':
                             bsdata = getsome(f"AES_{fpga_id}.bit")
                         elif self.target_name == 'Cryptech ecdsa256-v1 pmul':
@@ -505,7 +506,7 @@ def _con(self, scope=None, bsfile=None, force=False, fpga_id=None, defines_files
                     target_logger.warning(("FPGA Bitstream not configured or '%s' not a file." % str(bsfile)))
                 else:
                     starttime = datetime.now()
-                    status = self.fpga.FPGAProgram(open(bsfile, "rb"), exceptOnDoneFailure=False, prog_speed=prog_speed)
+                    status = self.fpga.FPGAProgram(bsfile, exceptOnDoneFailure=False, prog_speed=prog_speed)
                     stoptime = datetime.now()
                     if status:
                         target_logger.info('FPGA Config OK, time: %s' % str(stoptime - starttime))
@@ -533,13 +534,15 @@ def _con(self, scope=None, bsfile=None, force=False, fpga_id=None, defines_files
 
                 if bsfile is None:
                     if self.platform == 'ss2_ice40':
-                        from chipwhisperer.hardware.firmware.cwtargetice40 import getsome
+                        from ...hardware.firmware.open_fw import getsome_generator
+                        getsome = getsome_generator("cwtargetice40")
                         if self.target_name == 'AES':
                             bsfile = getsome(f"iCE40UP5K_SS2.bin")
                         else:
                             raise ValueError('Unknown target!')
                     else:
-                        from chipwhisperer.hardware.firmware.xc7a35 import getsome
+                        from ...hardware.firmware.open_fw import getsome_generator
+                        getsome = getsome_generator("xc7a35")
                         if self.target_name == 'AES':
                             bsfile = getsome(f"AES_cw312t_a35.bit")
                         elif self.target_name == 'Cryptech ecdsa256-v1 pmul':

software/chipwhisperer/capture/targets/CW310.py

@@ -148,8 +148,8 @@ def _con(self, scope=None, bsfile=None, force=False, fpga_id=None, defines_files
             if fpga_id is None:
                 verilog_defines = [self.default_verilog_defines_full_path]
             else:
-                from ...hardware.firmware.cw305 import getsome
-                verilog_defines = [getsome(self.default_verilog_defines)]
+                from ...hardware.firmware.open_fw import registers
+                verilog_defines = [registers("cw305")]
         else:
             verilog_defines = defines_files
         if slurp:

software/chipwhisperer/capture/targets/CW340.py

@@ -94,8 +94,8 @@ def _con(self, scope=None, bsfile=None, force=False, fpga_id=None, defines_files
             if fpga_id is None:
                 verilog_defines = [self.default_verilog_defines_full_path]
             else:
-                from ...hardware.firmware.cw305 import getsome
-                verilog_defines = [getsome(self.default_verilog_defines)]
+                from ...hardware.firmware.open_fw import registers
+                verilog_defines = [registers("cw305")]
         else:
             verilog_defines = defines_files
         if slurp:

software/chipwhisperer/hardware/firmware/open_fw.py

@@ -43,6 +43,15 @@ def registers(dev_name, filelike=True):
         return data
     pass
 
+def getsome_generator(dev_name):
+    def getsome(item, filelike=True):
+        with open(res_file_path(dev_name, item), "rb") as f:
+            data = f.read()
+            if filelike:
+                data = io.BytesIO(data)
+            return data
+    return getsome
+
 def _extract_file(getsome, item):
     data = getsome(item).read()
     with open(item, "wb") as f:

software/chipwhisperer/hardware/naeusb/programmer_neorv32.py

@@ -119,11 +119,13 @@ def load_ice40(self, bsfile=None, force_ice40type=None):
                 devtype = devtype[0].lower()
 
             if devtype == "ice40up5k":
-                from chipwhisperer.hardware.firmware.cwtargetice40 import getsome
+                # from chipwhisperer.hardware.firmware.cwtargetice40 import getsome
+                from ..firmware.open_fw import res_file_path
             else:
                 raise ValueError("Device type: %s. I don't have a pre-built FPGA bitstream for you (or connection bad)."%devtype)
 
-            bsdata = getsome("neorv32_iCE40CW312_MinimalBoot_directclk_7370KHz.bit").read()
+            # bsdata = getsome("neorv32_iCE40CW312_MinimalBoot_directclk_7370KHz.bit").read()
+            bsdata = open(res_file_path("neorv32_iCE40CW312_MinimalBoot_directclk_7370KHz.bit"), "rb").read()
         else:
             target_logger.info("ice40: Loading bitstream from %s"%bsfile)
             f = open(bsfile, "rb")