Expanding ARM32 Support

Source/Data/ARM32-Instructions.json

@@ -931,11 +931,11 @@
 			"OpcodeEncoding": [
 				{
 					"Condition": "[register][constant]",
-					"Encoding": "[arm-single-data-transfer-immediate],u=updir:status,rd=reg4:r,rn=reg4:o1,i=0,p=0,l=1,w=0,b=0,offset=imm12:o2"
+					"Encoding": "[arm-single-data-transfer-immediate],u=updir:status,rd=reg4:r,rn=reg4:o1,i=0,p=0,l=1,w=writeback:status,b=0,offset=imm12:o2"
 				},
 				{
 					"Condition": "[register][register]",
-					"Encoding": "[arm-single-data-transfer-shift-register],u=updir:status,rd=reg4:r,rn=reg4:o1,shiftamount=00000,shifttype=00,rm=reg4:o2,i=0,p=0,l=1,w=0,b=0"
+					"Encoding": "[arm-single-data-transfer-shift-register],u=updir:status,rd=reg4:r,rn=reg4:o1,shiftamount=00000,shifttype=00,rm=reg4:o2,i=0,p=0,l=1,w=writeback:status,b=0"
 				}
 			]
 		},
@@ -956,11 +956,11 @@
 			"OpcodeEncoding": [
 				{
 					"Condition": "[register][constant]",
-					"Encoding": "[arm-single-data-transfer-immediate],rd=reg4:r,rn=reg4:o1,i=0,p=0,l=1,w=0,b=1,u=updir:status,offset=imm12:o2"
+					"Encoding": "[arm-single-data-transfer-immediate],rd=reg4:r,rn=reg4:o1,i=0,p=0,l=1,w=writeback:status,b=1,u=updir:status,offset=imm12:o2"
 				},
 				{
 					"Condition": "[register][register]",
-					"Encoding": "[arm-single-data-transfer-shift-register],rd=reg4:r,rn=reg4:o1,shiftamount=00000,shifttype=00,rm=reg4:o2,i=0,p=0,l=1,w=0,b=1,u=updir:status"
+					"Encoding": "[arm-single-data-transfer-shift-register],rd=reg4:r,rn=reg4:o1,shiftamount=00000,shifttype=00,rm=reg4:o2,i=0,p=0,l=1,w=writeback:status,b=1,u=updir:status"
 				}
 			]
 		},
@@ -981,11 +981,11 @@
 			"OpcodeEncoding": [
 				{
 					"Condition": "[register][constant]",
-					"Encoding": "[arm-halfword-data-transfer-immediate],rd=reg4:r,rn=reg4:o1,i=1,p=0,l=1,w=0,b=0,offsethigh=imm4hn:o2,offsetlow=imm4:o2,u=updir:status,s=0,h=1"
+					"Encoding": "[arm-halfword-data-transfer-immediate],rd=reg4:r,rn=reg4:o1,i=1,p=0,l=1,w=writeback:status,b=0,offsethigh=imm4hn:o2,offsetlow=imm4:o2,u=updir:status,s=0,h=1"
 				},
 				{
 					"Condition": "[register][register]",
-					"Encoding": "[arm-halfword-data-transfer-register],rd=reg4:r,rn=reg4:o1,h=1,rm=reg4:o2,i=0,p=0,l=1,w=0,b=1,u=updir:status,s=0,h=1"
+					"Encoding": "[arm-halfword-data-transfer-register],rd=reg4:r,rn=reg4:o1,h=1,rm=reg4:o2,i=0,p=0,l=1,w=writeback:status,b=1,u=updir:status,s=0,h=1"
 				}
 			]
 		},
@@ -1006,11 +1006,11 @@
 			"OpcodeEncoding": [
 				{
 					"Condition": "[register][constant]",
-					"Encoding": "[arm-halfword-data-transfer-immediate],rd=reg4:r,rn=reg4:o1,i=1,p=0,l=1,w=0,b=1,offsethigh=imm4hn:o2,offsetlow=imm4:o2,u=updir:status,s=1,h=1"
+					"Encoding": "[arm-halfword-data-transfer-immediate],rd=reg4:r,rn=reg4:o1,i=1,p=0,l=1,w=writeback:status,b=1,offsethigh=imm4hn:o2,offsetlow=imm4:o2,u=updir:status,s=1,h=1"
 				},
 				{
 					"Condition": "[register][register]",
-					"Encoding": "[arm-halfword-data-transfer-register],rd=reg4:r,rn=reg4:o1,h=1,rm=reg4:o2,i=0,p=0,l=1,w=0,b=0,u=updir:status,s=1,h=1"
+					"Encoding": "[arm-halfword-data-transfer-register],rd=reg4:r,rn=reg4:o1,h=1,rm=reg4:o2,i=0,p=0,l=1,w=writeback:status,b=0,u=updir:status,s=1,h=1"
 				}
 			]
 		},
@@ -1031,11 +1031,11 @@
 			"OpcodeEncoding": [
 				{
 					"Condition": "[register][constant]",
-					"Encoding": "[arm-halfword-data-transfer-immediate],rd=reg4:r,rn=reg4:o1,i=1,p=0,l=1,w=0,b=1,offsethigh=imm4hn:o2,offsetlow=imm4:o2,u=updir:status,s=1,h=0"
+					"Encoding": "[arm-halfword-data-transfer-immediate],rd=reg4:r,rn=reg4:o1,i=1,p=0,l=1,w=writeback:status,b=1,offsethigh=imm4hn:o2,offsetlow=imm4:o2,u=updir:status,s=1,h=0"
 				},
 				{
 					"Condition": "[register][register]",
-					"Encoding": "[arm-halfword-data-transfer-register],rd=reg4:r,rn=reg4:o1,rm=reg4:o2,i=0,p=0,l=1,w=0,b=0,u=updir:status,s=1,h=0"
+					"Encoding": "[arm-halfword-data-transfer-register],rd=reg4:r,rn=reg4:o1,rm=reg4:o2,i=0,p=0,l=1,w=writeback:status,b=0,u=updir:status,s=1,h=0"
 				}
 			]
 		},
@@ -1056,11 +1056,11 @@
 			"OpcodeEncoding": [
 				{
 					"Condition": "[register][constant][register]",
-					"Encoding": "[arm-single-data-transfer-immediate],rd=reg4:o3,rn=reg4:o1,i=0,p=0,l=0,w=0,b=0,u=updir:status,offset=imm12:o2"
+					"Encoding": "[arm-single-data-transfer-immediate],rd=reg4:o3,rn=reg4:o1,i=0,p=0,l=0,w=writeback:status,b=0,u=updir:status,offset=imm12:o2"
 				},
 				{
 					"Condition": "[register][register][register]",
-					"Encoding": "[arm-single-data-transfer-shift-register],rd=reg4:o3,rn=reg4:o1,i=0,p=0,l=0,w=0,b=0,u=updir:status,shiftamount=00000,shifttype=00,rm=reg4:o2"
+					"Encoding": "[arm-single-data-transfer-shift-register],rd=reg4:o3,rn=reg4:o1,i=0,p=0,l=0,w=writeback:status,b=0,u=updir:status,shiftamount=00000,shifttype=00,rm=reg4:o2"
 				}
 			]
 		},
@@ -1081,11 +1081,11 @@
 			"OpcodeEncoding": [
 				{
 					"Condition": "[register][constant][register]",
-					"Encoding": "[arm-single-data-transfer-immediate],rd=reg4:o3,rn=reg4:o1,i=0,p=0,l=0,w=0,b=1,u=updir:status,offset=imm12:o2"
+					"Encoding": "[arm-single-data-transfer-immediate],rd=reg4:o3,rn=reg4:o1,i=0,p=0,l=0,w=writeback:status,b=1,u=updir:status,offset=imm12:o2"
 				},
 				{
 					"Condition": "[register][register][register]",
-					"Encoding": "[arm-single-data-transfer-shift-register],rd=reg4:o3,rn=reg4:o1,i=0,p=0,l=0,w=0,b=1,u=updir:status,shiftamount=00000,shifttype=00,rm=reg4:o2"
+					"Encoding": "[arm-single-data-transfer-shift-register],rd=reg4:o3,rn=reg4:o1,i=0,p=0,l=0,w=writeback:status,b=1,u=updir:status,shiftamount=00000,shifttype=00,rm=reg4:o2"
 				}
 			]
 		},
@@ -1106,11 +1106,11 @@
 			"OpcodeEncoding": [
 				{
 					"Condition": "[register][constant][register]",
-					"Encoding": "[arm-halfword-data-transfer-immediate],rd=reg4:o3,rn=reg4:o1,i=1,p=0,l=0,w=0,b=0,offsethigh=imm4hn:o2,offsetlow=imm4:o2,u=updir:status,s=0,h=1"
+					"Encoding": "[arm-halfword-data-transfer-immediate],rd=reg4:o3,rn=reg4:o1,i=1,p=0,l=0,w=writeback:status,b=0,offsethigh=imm4hn:o2,offsetlow=imm4:o2,u=updir:status,s=0,h=1"
 				},
 				{
 					"Condition": "[register][register][register]",
-					"Encoding": "[arm-single-data-transfer-immediate],rd=reg4:o3,rn=reg4:o1,rm=reg4:o2,i=0,p=0,l=0,w=0,b=1,u=updir:status,s=0,h=1"
+					"Encoding": "[arm-single-data-transfer-immediate],rd=reg4:o3,rn=reg4:o1,rm=reg4:o2,i=0,p=0,l=0,w=writeback:status,b=1,u=updir:status,s=0,h=1"
 				}
 			]
 		},
@@ -1131,11 +1131,11 @@
 			"OpcodeEncoding": [
 				{
 					"Condition": "[register][constant][register]",
-					"Encoding": "[arm-halfword-data-transfer-immediate],rd=reg4:o3,rn=reg4:o1,i=1,p=0,l=0,w=0,b=1,offsethigh=imm4hn:o2,offsetlow=imm4:o2,u=updir:status,s=1,h=1"
+					"Encoding": "[arm-halfword-data-transfer-immediate],rd=reg4:o3,rn=reg4:o1,i=1,p=0,l=0,w=writeback:status,b=1,offsethigh=imm4hn:o2,offsetlow=imm4:o2,u=updir:status,s=1,h=1"
 				},
 				{
 					"Condition": "[register][register][register]",
-					"Encoding": "[arm-halfword-data-transfer-register],rd=reg4:o3,rn=reg4:o1,rm=reg4:o2,i=0,p=0,l=0,w=0,b=0,u=updir:status,s=1,h=1"
+					"Encoding": "[arm-halfword-data-transfer-register],rd=reg4:o3,rn=reg4:o1,rm=reg4:o2,i=0,p=0,l=0,w=writeback:status,b=0,u=updir:status,s=1,h=1"
 				}
 			]
 		},
@@ -1156,11 +1156,11 @@
 			"OpcodeEncoding": [
 				{
 					"Condition": "[register][constant][register]",
-					"Encoding": "[arm-halfword-data-transfer-immediate],rd=reg4:o3,rn=reg4:o1,i=1,p=0,l=0,w=0,b=1,offsethigh=imm4hn:o2,offsetlow=imm4:o2,u=updir:status,s=1,h=0"
+					"Encoding": "[arm-halfword-data-transfer-immediate],rd=reg4:o3,rn=reg4:o1,i=1,p=0,l=0,w=writeback:status,b=1,offsethigh=imm4hn:o2,offsetlow=imm4:o2,u=updir:status,s=1,h=0"
 				},
 				{
 					"Condition": "[register][register][register]",
-					"Encoding": "[arm-halfword-data-transfer-register],rd=reg4:o3,rn=reg4:o1,rm=reg4:o2,i=0,p=0,l=0,w=0,b=0,u=updir:status,s=1,h=0"
+					"Encoding": "[arm-halfword-data-transfer-register],rd=reg4:o3,rn=reg4:o1,rm=reg4:o2,i=0,p=0,l=0,w=writeback:status,b=0,u=updir:status,s=1,h=0"
 				}
 			]
 		},
@@ -1366,7 +1366,7 @@
 			"OpcodeEncoding": [
 				{
 					"Condition": "[register][constant][constant]",
-					"Encoding": "[arm-block-transfer],p=0,u=updir:status,s=imm1:o2,w=0,l=1,rn=reg4:o1,list=imm16:o2"
+					"Encoding": "[arm-block-transfer],p=0,u=updir:status,s=imm1:o2,w=writeback:status,l=1,rn=reg4:o1,list=imm16:o2"
 				}
 			]
 		},
@@ -1386,7 +1386,11 @@
 			"OpcodeEncoding": [
 				{
 					"Condition": "[register][constant][constant]",
-					"Encoding": "[arm-block-transfer],p=1,u=updir:status,s=imm1:o2,w=0,l=0,rn=reg4:o1,list=imm16:o2"
+					"Encoding": "[arm-block-transfer],p=1,u=updir:status,s=imm1:o2,w=writeback:status,l=0,rn=reg4:o1,list=imm16:o3"
+				},
+				{
+					"Condition": "[register][constant][register]",
+					"Encoding": "[arm-block-transfer],p=1,u=updir:status,s=imm1:o2,w=writeback:status,l=0,rn=reg4:o1,list=reg16pow2:o3"
 				}
 			]
 		},

Source/Docs/settings-options.rst

@@ -13,6 +13,7 @@ Compiler Settings
 
     Compiler.Platform,"Platform x86, x64, ARM32, ARM64"
     Compiler.BaseAddress,Base address of the compiled application
+	Compiler.InitialStackAddress,Intial stack's starting address (note the stack grows in the downward direction).
     Compiler.TraceLevel,Trace level for debugging
     Compiler.MethodScanner,"If true, enable the experimental method scanner"
     Compiler.Multithreading,"If true, enables multithreading during compiling process"

Source/Mosa.BareMetal.HelloWorld/Apps/BootInfo.cs

@@ -15,14 +15,20 @@ public class BootInfo : IApp
 
 	public void Execute()
 	{
-		Console.WriteLine("Command line           : " + NullTermString(Multiboot.V2.CommandLinePointer));
-		Console.WriteLine("Bootloader name        : " + NullTermString(Multiboot.V2.BootloaderNamePointer));
+		Console.WriteLine("Command line           : " + NullTermString(Multiboot.V2.CommandLine));
+		Console.WriteLine("Bootloader name        : " + NullTermString(Multiboot.V2.BootloaderName));
 		Console.WriteLine("Memory lower           : " + Multiboot.V2.MemoryLower / 1024 + " MiB");
 		Console.WriteLine("Memory upper           : " + Multiboot.V2.MemoryUpper / 1024 + " MiB");
-		Console.WriteLine("Memory map entries     : " + Multiboot.V2.Entries);
-		Console.WriteLine("Framebuffer available  : " + Multiboot.V2.FramebufferAvailable);
-		if (Multiboot.V2.FramebufferAvailable) Console.WriteLine("Framebuffer resolution : " + Multiboot.V2.Framebuffer.Width + "x" + Multiboot.V2.Framebuffer.Height);
-		Console.WriteLine("ACPI version           : " + (Multiboot.V2.ACPIv2 ? "2" : "1"));
+		Console.WriteLine("Memory map entries     : " + Multiboot.V2.MemoryMapEntries);
+		Console.WriteLine("Framebuffer available  : " + !Multiboot.V2.FrameBuffer.IsNull);
+
+		if (!Multiboot.V2.FrameBuffer.IsNull)
+		{
+			Console.WriteLine("Framebuffer resolution : " + Multiboot.V2.FrameBufferWidth + "x" + Multiboot.V2.FrameBufferHeight);
+		}
+
+		Console.WriteLine("RSDPv1 version           : " + !Multiboot.V2.RSDPv1.IsNull);
+		Console.WriteLine("RSDPv2 version           : " + !Multiboot.V2.RSDPv2.IsNull);
 	}
 
 	private readonly StringBuilder Builder = new();

Source/Mosa.Compiler.ARM32/ARM32Instruction.cs

@@ -33,7 +33,7 @@ protected ARM32Instruction(byte resultCount, byte operandCount)
 	/// </value>
 	public override string FamilyName => "ARM32";
 
-	public static byte GetConditionCode(ConditionCode condition)
+	protected static byte GetConditionCode(ConditionCode condition)
 	{
 		return condition switch
 		{
@@ -62,4 +62,9 @@ public static byte GetConditionCode(ConditionCode condition)
 			_ => throw new NotSupportedException()
 		};
 	}
+
+	protected static uint ToPower2(uint r)
+	{
+		return (uint)(1 << (int)r);
+	}
 }

Source/Mosa.Compiler.ARM32/CompilerStages/MultibootStage.cs

@@ -0,0 +1,55 @@
+// Copyright (c) MOSA Project. Licensed under the New BSD License.
+
+using Mosa.Compiler.Framework;
+
+namespace Mosa.Compiler.ARM32.CompilerStages;
+
+public sealed class MultibootStage : Framework.Platform.BaseMultibootStage
+{
+	protected override void CreateMultibootMethod()
+	{
+		var basicBlocks = new BasicBlocks();
+
+		var methodCompiler = new MethodCompiler(Compiler, MultibootMethod, basicBlocks, 0);
+		methodCompiler.MethodData.DoNotInline = true;
+
+		var transform = new Transform();
+		transform.SetCompiler(Compiler);
+		transform.SetMethodCompiler(methodCompiler);
+
+		var initializeMethod = TypeSystem.GetMethod("Mosa.Runtime.StartUp", "Initialize");
+		var entryPoint = Operand.CreateLabel(initializeMethod, Architecture.Is32BitPlatform);
+
+		var lr = transform.PhysicalRegisters.Allocate64(CPURegister.LR);
+		var sp = transform.PhysicalRegisters.Allocate64(CPURegister.SP);
+
+		var d10 = transform.PhysicalRegisters.Allocate64(CPURegister.d10);
+		var d11 = transform.PhysicalRegisters.Allocate64(CPURegister.d11);
+
+		var stackLocation = Operand.CreateConstant32(MosaSettings.InitialStackLocation);
+
+		var prologueBlock = basicBlocks.CreatePrologueBlock();
+
+		var context = new Context(prologueBlock);
+
+		// Set stack location
+		context.AppendInstruction(ARM32.Movw, sp, stackLocation);
+		context.AppendInstruction(ARM32.Movt, sp, sp, stackLocation);
+
+		// Create stack sentinel
+		context.AppendInstruction(ARM32.Movw, lr, Operand.Constant32_0);
+		context.AppendInstruction(ARM32.Stm, null, sp, Operand.Constant32_0, lr);
+		context.AppendInstruction(ARM32.Stm, null, sp, Operand.Constant32_0, lr);
+
+		//// Push registers onto the new stack
+		context.AppendInstruction(ARM32.Mov, lr, sp);
+		context.AppendInstruction(ARM32.Stm, null, sp, Operand.Constant32_0, Operand.Constant32_FFFF);
+		context.AppendInstruction(ARM32.Stm, null, sp, Operand.Constant32_0, sp);
+
+		// Call entry point
+		context.AppendInstruction(ARM32.Bl, null, entryPoint);
+		context.AppendInstruction(ARM32.Pop, null, Operand.Constant32_0);
+
+		Compiler.CompileMethod(transform);
+	}
+}

Source/Mosa.Compiler.ARM32/Instructions/Ldm.cs

@@ -28,7 +28,7 @@ public override void Emit(Node node, OpcodeEncoder opcodeEncoder)
 			opcodeEncoder.Append1Bit(0b0);
 			opcodeEncoder.Append1Bit(node.IsUpDirection ? 1 : 0);
 			opcodeEncoder.Append1BitImmediate(node.Operand2);
-			opcodeEncoder.Append1Bit(0b0);
+			opcodeEncoder.Append1Bit(node.IsWriteback ? 1 : 0);
 			opcodeEncoder.Append1Bit(0b1);
 			opcodeEncoder.Append4Bits(node.Operand1.Register.RegisterCode);
 			opcodeEncoder.Append16BitImmediate(node.Operand2);

Source/Mosa.Compiler.ARM32/Instructions/Ldr16.cs

@@ -28,7 +28,7 @@ public override void Emit(Node node, OpcodeEncoder opcodeEncoder)
 			opcodeEncoder.Append1Bit(0b0);
 			opcodeEncoder.Append1Bit(node.IsUpDirection ? 1 : 0);
 			opcodeEncoder.Append1Bit(0b1);
-			opcodeEncoder.Append1Bit(0b0);
+			opcodeEncoder.Append1Bit(node.IsWriteback ? 1 : 0);
 			opcodeEncoder.Append1Bit(0b1);
 			opcodeEncoder.Append4Bits(node.Operand1.Register.RegisterCode);
 			opcodeEncoder.Append4Bits(node.Result.Register.RegisterCode);
@@ -48,7 +48,7 @@ public override void Emit(Node node, OpcodeEncoder opcodeEncoder)
 			opcodeEncoder.Append1Bit(0b0);
 			opcodeEncoder.Append1Bit(node.IsUpDirection ? 1 : 0);
 			opcodeEncoder.Append1Bit(0b0);
-			opcodeEncoder.Append1Bit(0b0);
+			opcodeEncoder.Append1Bit(node.IsWriteback ? 1 : 0);
 			opcodeEncoder.Append1Bit(0b1);
 			opcodeEncoder.Append4Bits(node.Operand1.Register.RegisterCode);
 			opcodeEncoder.Append4Bits(node.Result.Register.RegisterCode);

Source/Mosa.Compiler.ARM32/Instructions/Ldr32.cs

@@ -29,7 +29,7 @@ public override void Emit(Node node, OpcodeEncoder opcodeEncoder)
 			opcodeEncoder.Append1Bit(0b0);
 			opcodeEncoder.Append1Bit(node.IsUpDirection ? 1 : 0);
 			opcodeEncoder.Append1Bit(0b0);
-			opcodeEncoder.Append1Bit(0b0);
+			opcodeEncoder.Append1Bit(node.IsWriteback ? 1 : 0);
 			opcodeEncoder.Append1Bit(0b1);
 			opcodeEncoder.Append4Bits(node.Operand1.Register.RegisterCode);
 			opcodeEncoder.Append4Bits(node.Result.Register.RegisterCode);
@@ -45,7 +45,7 @@ public override void Emit(Node node, OpcodeEncoder opcodeEncoder)
 			opcodeEncoder.Append1Bit(0b0);
 			opcodeEncoder.Append1Bit(node.IsUpDirection ? 1 : 0);
 			opcodeEncoder.Append1Bit(0b0);
-			opcodeEncoder.Append1Bit(0b0);
+			opcodeEncoder.Append1Bit(node.IsWriteback ? 1 : 0);
 			opcodeEncoder.Append1Bit(0b1);
 			opcodeEncoder.Append4Bits(node.Operand1.Register.RegisterCode);
 			opcodeEncoder.Append4Bits(node.Result.Register.RegisterCode);

Source/Mosa.Compiler.ARM32/Instructions/Ldr8.cs

@@ -29,7 +29,7 @@ public override void Emit(Node node, OpcodeEncoder opcodeEncoder)
 			opcodeEncoder.Append1Bit(0b0);
 			opcodeEncoder.Append1Bit(node.IsUpDirection ? 1 : 0);
 			opcodeEncoder.Append1Bit(0b1);
-			opcodeEncoder.Append1Bit(0b0);
+			opcodeEncoder.Append1Bit(node.IsWriteback ? 1 : 0);
 			opcodeEncoder.Append1Bit(0b1);
 			opcodeEncoder.Append4Bits(node.Operand1.Register.RegisterCode);
 			opcodeEncoder.Append4Bits(node.Result.Register.RegisterCode);
@@ -45,7 +45,7 @@ public override void Emit(Node node, OpcodeEncoder opcodeEncoder)
 			opcodeEncoder.Append1Bit(0b0);
 			opcodeEncoder.Append1Bit(node.IsUpDirection ? 1 : 0);
 			opcodeEncoder.Append1Bit(0b1);
-			opcodeEncoder.Append1Bit(0b0);
+			opcodeEncoder.Append1Bit(node.IsWriteback ? 1 : 0);
 			opcodeEncoder.Append1Bit(0b1);
 			opcodeEncoder.Append4Bits(node.Operand1.Register.RegisterCode);
 			opcodeEncoder.Append4Bits(node.Result.Register.RegisterCode);

Source/Mosa.Compiler.ARM32/Instructions/LdrS16.cs

@@ -28,7 +28,7 @@ public override void Emit(Node node, OpcodeEncoder opcodeEncoder)
 			opcodeEncoder.Append1Bit(0b0);
 			opcodeEncoder.Append1Bit(node.IsUpDirection ? 1 : 0);
 			opcodeEncoder.Append1Bit(0b1);
-			opcodeEncoder.Append1Bit(0b0);
+			opcodeEncoder.Append1Bit(node.IsWriteback ? 1 : 0);
 			opcodeEncoder.Append1Bit(0b1);
 			opcodeEncoder.Append4Bits(node.Operand1.Register.RegisterCode);
 			opcodeEncoder.Append4Bits(node.Result.Register.RegisterCode);
@@ -48,7 +48,7 @@ public override void Emit(Node node, OpcodeEncoder opcodeEncoder)
 			opcodeEncoder.Append1Bit(0b0);
 			opcodeEncoder.Append1Bit(node.IsUpDirection ? 1 : 0);
 			opcodeEncoder.Append1Bit(0b0);
-			opcodeEncoder.Append1Bit(0b0);
+			opcodeEncoder.Append1Bit(node.IsWriteback ? 1 : 0);
 			opcodeEncoder.Append1Bit(0b1);
 			opcodeEncoder.Append4Bits(node.Operand1.Register.RegisterCode);
 			opcodeEncoder.Append4Bits(node.Result.Register.RegisterCode);

Source/Mosa.Compiler.ARM32/Instructions/LdrS8.cs

@@ -28,7 +28,7 @@ public override void Emit(Node node, OpcodeEncoder opcodeEncoder)
 			opcodeEncoder.Append1Bit(0b0);
 			opcodeEncoder.Append1Bit(node.IsUpDirection ? 1 : 0);
 			opcodeEncoder.Append1Bit(0b1);
-			opcodeEncoder.Append1Bit(0b0);
+			opcodeEncoder.Append1Bit(node.IsWriteback ? 1 : 0);
 			opcodeEncoder.Append1Bit(0b1);
 			opcodeEncoder.Append4Bits(node.Operand1.Register.RegisterCode);
 			opcodeEncoder.Append4Bits(node.Result.Register.RegisterCode);
@@ -48,7 +48,7 @@ public override void Emit(Node node, OpcodeEncoder opcodeEncoder)
 			opcodeEncoder.Append1Bit(0b0);
 			opcodeEncoder.Append1Bit(node.IsUpDirection ? 1 : 0);
 			opcodeEncoder.Append1Bit(0b0);
-			opcodeEncoder.Append1Bit(0b0);
+			opcodeEncoder.Append1Bit(node.IsWriteback ? 1 : 0);
 			opcodeEncoder.Append1Bit(0b1);
 			opcodeEncoder.Append4Bits(node.Operand1.Register.RegisterCode);
 			opcodeEncoder.Append4Bits(node.Result.Register.RegisterCode);

Source/Mosa.Compiler.ARM32/Instructions/Stm.cs

@@ -28,10 +28,24 @@ public override void Emit(Node node, OpcodeEncoder opcodeEncoder)
 			opcodeEncoder.Append1Bit(0b1);
 			opcodeEncoder.Append1Bit(node.IsUpDirection ? 1 : 0);
 			opcodeEncoder.Append1BitImmediate(node.Operand2);
+			opcodeEncoder.Append1Bit(node.IsWriteback ? 1 : 0);
 			opcodeEncoder.Append1Bit(0b0);
+			opcodeEncoder.Append4Bits(node.Operand1.Register.RegisterCode);
+			opcodeEncoder.Append16BitImmediate(node.Operand3);
+			return;
+		}
+
+		if (node.Operand1.IsPhysicalRegister && node.Operand2.IsConstant && node.Operand3.IsPhysicalRegister)
+		{
+			opcodeEncoder.Append4Bits(GetConditionCode(node.ConditionCode));
+			opcodeEncoder.Append3Bits(0b100);
+			opcodeEncoder.Append1Bit(0b1);
+			opcodeEncoder.Append1Bit(node.IsUpDirection ? 1 : 0);
+			opcodeEncoder.Append1BitImmediate(node.Operand2);
+			opcodeEncoder.Append1Bit(node.IsWriteback ? 1 : 0);
 			opcodeEncoder.Append1Bit(0b0);
 			opcodeEncoder.Append4Bits(node.Operand1.Register.RegisterCode);
-			opcodeEncoder.Append16BitImmediate(node.Operand2);
+			opcodeEncoder.Append16Bits(ToPower2(node.Operand3.Register.RegisterCode));
 			return;
 		}