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Expanding ARM32 + ARM64 Support (#1183)
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* - ARM64

* - ARM64

* - ARM64

* - ARM64

* - ARM64

* - WIP

* - WIP

* - WIP

* - WIP

* - WIP

* - WIP

* - WIP
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@tgiphil
tgiphil authored Dec 15, 2023
1 parent 029ae4d commit a5f4ee8
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Showing 541 changed files with 4,593 additions and 2,410 deletions.
543 changes: 90 additions & 453 deletions Source/Data/ARM32-Instructions.json
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170 changes: 170 additions & 0 deletions Source/Data/ARM64-Instructions.json
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Expand Up @@ -25,6 +25,28 @@
}
]
},
{
"Name": "Adc32",
"Commutative": "true",
"FamilyName": "ARM64",
"FlagsCleared": "",
"FlagsModified": "",
"FlagsSet": "",
"FlagsUnchanged": "",
"FlagsUndefined": "",
"FlagsUsed": "",
"OperandCount": 2,
"ResultCount": 1,
"Description": "Add with carry",
"OpcodeEncodingAppend": "sf=0,opcode=11010000,op=0",
"OpcodeEncoding": [
{
"Condition": "[register][register]",
"Encoding": "[sf]|[op]|[s]|[opcode]|[rm]|000000|[rn]|[rd]",
"Append": "rd=reg5:r,rn=reg5:o1,rm=reg5:o2,s=setflag:status"
}
]
},
{
"Name": "Adc64",
"Commutative": "true",
Expand All @@ -47,6 +69,33 @@
}
]
},
{
"Name": "Add32",
"Commutative": "true",
"FamilyName": "ARM64",
"FlagsCleared": "",
"FlagsModified": "",
"FlagsSet": "",
"FlagsUnchanged": "",
"FlagsUndefined": "",
"FlagsUsed": "",
"OperandCount": 2,
"ResultCount": 1,
"Description": "Add with carry",
"OpcodeEncodingAppend": "sf=0,op=0,rd=reg5:r,s=setflag:status",
"OpcodeEncoding": [
{
"Condition": "[register][register]",
"Encoding": "[sf]|[op]|[s]|[opcode]|[rm]|[option]|[imm3]|[rn]|[rd]",
"Append": "opcode=01011001,rn=reg5:o1,rm=reg5:o2,option=000,imm3=000"
},
{
"Condition": "[register][constant_imm32u]",
"Encoding": "[sf]|[op]|[s]|[opcode]|[shift]|[imm12]|[rn]|[rd]",
"Append": "opcode=100010,rn=reg5:o1,shift=0,imm12=imm12:o2"
}
]
},
{
"Name": "Add64",
"Commutative": "true",
Expand All @@ -73,6 +122,127 @@
"Append": "opcode=100010,rn=reg5:o1,shift=0,imm12=imm12:o2"
}
]
},
{
"Name": "And64",
"Commutative": "true",
"FamilyName": "ARM64",
"FlagsCleared": "",
"FlagsModified": "",
"FlagsSet": "",
"FlagsUnchanged": "NZCV",
"FlagsUndefined": "",
"FlagsUsed": "",
"OperandCount": 2,
"ResultCount": 1,
"Description": "And",
"OpcodeEncodingAppend": "sf=1,opc=00,rd=reg5:r",
"OpcodeEncoding": [
{
"Condition": "[register][register]",
"Encoding": "[sf]|[opc]|[opcode]|[shift]|[n]|[rm]|[imm6]|[rn]|[rd]",
"Append": "opcode=01010,shift=00,n=0,imm6=000000,rn=reg5:o1,rm=reg5:o2"
}
]
},
{
"Name": "And32",
"Commutative": "true",
"FamilyName": "ARM64",
"FlagsCleared": "",
"FlagsModified": "",
"FlagsSet": "",
"FlagsUnchanged": "NZCV",
"FlagsUndefined": "",
"FlagsUsed": "",
"OperandCount": 2,
"ResultCount": 1,
"Description": "And",
"OpcodeEncodingAppend": "sf=0,opc=00,rd=reg5:r",
"OpcodeEncoding": [
{
"Condition": "[register][register]",
"Encoding": "[sf]|[opc]|[opcode]|[shift]|[n]|[rm]|[imm6]|[rn]|[rd]",
"Append": "opcode=01010,shift=00,n=0,imm6=000000,rn=reg5:o1,rm=reg5:o2"
}
]
},
{
"Name": "Asr32",
"Commutative": "false",
"FamilyName": "ARM64",
"FlagsCleared": "",
"FlagsModified": "",
"FlagsSet": "",
"FlagsUnchanged": "NZCV",
"FlagsUndefined": "",
"FlagsUsed": "",
"OperandCount": 2,
"ResultCount": 1,
"Description": "Arithmetic Shift Right",
"OpcodeEncodingAppend": "sf=0,opc=00,rd=reg5:r",
"OpcodeEncoding": [
{
"Condition": "[register][constant]",
"Encoding": "[sf]|[opc]|[opcode]|0|[shift]|011111|[rn]|[rd]",
"Append": "opcode=100110,shift=imm6:o2,rn=reg5:o1"
},
{
"Condition": "[register][register]",
"Encoding": "[sf]|[opc]|[opcode]|[rm]|00101|10|[rn]|[rd]",
"Append": "opcode=11010110,rm=reg5:o2,rn=reg5:o1"
}
]
},
{
"Name": "Asr64",
"Commutative": "false",
"FamilyName": "ARM64",
"FlagsCleared": "",
"FlagsModified": "",
"FlagsSet": "",
"FlagsUnchanged": "NZCV",
"FlagsUndefined": "",
"FlagsUsed": "",
"OperandCount": 2,
"ResultCount": 1,
"Description": "Arithmetic Shift Right",
"OpcodeEncodingAppend": "sf=1,opc=00,rd=reg5:r",
"OpcodeEncoding": [
{
"Condition": "[register][constant]",
"Encoding": "[sf]|[opc]|[opcode]|[shift]|111111|[rn]|[rd]",
"Append": "opcode=100110,shift=imm7:o2,rn=reg5:o1"
},
{
"Condition": "[register][register]",
"Encoding": "[sf]|[opc]|[opcode]|[rm]|00101|10|[rn]|[rd]",
"Append": "opcode=11010110,rm=reg5:o2,rn=reg5:o1"
}
]
},
{
"Name": "B",
"Commutative": "true",
"FamilyName": "ARM32",
"FlagsCleared": "",
"FlagsModified": "",
"FlagsSet": "",
"FlagsUnchanged": "NZCV",
"FlagsUndefined": "",
"FlagsUsed": "",
"FlowControl": "ConditionalBranch",
"OperandCount": 2,
"ResultCount": 1,
"Description": "Unconditional branch",
"OpcodeEncodingAppend": "",
"OpcodeEncoding": [
{
"Condition": "[constant]",
"Encoding": "000101|[imm26]",
"Append": "imm26=rel26x4:label"
}
]
}
]
}
34 changes: 34 additions & 0 deletions Source/Mosa.BareMetal.TestWorld.ARM32/Boot.cs
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@@ -0,0 +1,34 @@
// Copyright (c) MOSA Project. Licensed under the New BSD License.

using System;
using Mosa.Kernel.BareMetal;
using Mosa.UnitTests.Optimization;

namespace Mosa.BareMetal.TestWorld.ARM32;

public static class Boot
{
public static void Main()
{
Debug.WriteLine("Boot::Main()");

Console.BackgroundColor = ConsoleColor.Blue;
Console.ForegroundColor = ConsoleColor.White;
Console.Clear();
Console.WriteLine("Mosa.BareMetal.TextWorld.ARM32");
Console.WriteLine();

Division.DivisionBy7(254u);

// Will never get here!
Debug.WriteLine("ERROR: Thread Start Failure");
Debug.Fatal();
}

private static int counter = 0;

public static void ForceInclude()
{
Mosa.Kernel.BareMetal.ARM32.PlatformPlug.ForceInclude();
}
}
15 changes: 15 additions & 0 deletions Source/Mosa.BareMetal.TestWorld.ARM32/Mosa.BareMetal.TestWorld.ARM32.csproj
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Original file line number Diff line number Diff line change
@@ -0,0 +1,15 @@
<Project Sdk="Microsoft.NET.Sdk">

<PropertyGroup>
<OutputType>Exe</OutputType>
</PropertyGroup>

<Import Project="../Mosa.BareMetal.targets" />

<ItemGroup>
<ProjectReference Include="..\Mosa.BareMetal.TestWorld\Mosa.BareMetal.TestWorld.csproj" />
<ProjectReference Include="..\Mosa.Kernel.BareMetal.ARM32\Mosa.Kernel.BareMetal.ARM32.csproj" />
<ProjectReference Include="..\Mosa.UnitTests\Mosa.UnitTests.csproj" />
</ItemGroup>

</Project>
42 changes: 14 additions & 28 deletions Source/Mosa.Compiler.ARM32/ARM32.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -95,32 +95,18 @@ public static class ARM32
public static readonly BaseInstruction Lsr = new Lsr();
public static readonly BaseInstruction Asr = new Asr();
public static readonly BaseInstruction Ror = new Ror();
public static readonly BaseInstruction Adf = new Adf();
public static readonly BaseInstruction Muf = new Muf();
public static readonly BaseInstruction Suf = new Suf();
public static readonly BaseInstruction Rsf = new Rsf();
public static readonly BaseInstruction Dvr = new Dvr();
public static readonly BaseInstruction Dvf = new Dvf();
public static readonly BaseInstruction Rmf = new Rmf();
public static readonly BaseInstruction Fml = new Fml();
public static readonly BaseInstruction Fdv = new Fdv();
public static readonly BaseInstruction Frd = new Frd();
public static readonly BaseInstruction Mvf = new Mvf();
public static readonly BaseInstruction Mnf = new Mnf();
public static readonly BaseInstruction Abs = new Abs();
public static readonly BaseInstruction Rnd = new Rnd();
public static readonly BaseInstruction Sqt = new Sqt();
public static readonly BaseInstruction Flt = new Flt();
public static readonly BaseInstruction Fix = new Fix();
public static readonly BaseInstruction Wfs = new Wfs();
public static readonly BaseInstruction Rfs = new Rfs();
public static readonly BaseInstruction Wfc = new Wfc();
public static readonly BaseInstruction Rfc = new Rfc();
public static readonly BaseInstruction Cmf = new Cmf();
public static readonly BaseInstruction Cnf = new Cnf();
public static readonly BaseInstruction Cmfe = new Cmfe();
public static readonly BaseInstruction Cnfe = new Cnfe();
public static readonly BaseInstruction Ldf = new Ldf();
public static readonly BaseInstruction Stf = new Stf();
public static readonly BaseInstruction Fmov = new Fmov();
public static readonly BaseInstruction VAdd = new VAdd();
public static readonly BaseInstruction VSub = new VSub();
public static readonly BaseInstruction VMul = new VMul();
public static readonly BaseInstruction VDiv = new VDiv();
public static readonly BaseInstruction VMov = new VMov();
public static readonly BaseInstruction VMov2FP = new VMov2FP();
public static readonly BaseInstruction VMov2U = new VMov2U();
public static readonly BaseInstruction VMov2S = new VMov2S();
public static readonly BaseInstruction VCmp = new VCmp();
public static readonly BaseInstruction VMrs = new VMrs();
public static readonly BaseInstruction VMrs_APSR = new VMrs_APSR();
public static readonly BaseInstruction VMsr = new VMsr();
public static readonly BaseInstruction VLdr = new VLdr();
public static readonly BaseInstruction VStr = new VStr();
}
35 changes: 12 additions & 23 deletions Source/Mosa.Compiler.ARM32/Architecture.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -117,11 +117,18 @@ public sealed class Architecture : BaseArchitecture
/// </summary>
public override PhysicalRegister ProgramCounter => CPURegister.PC;

/// <summary>
/// Updates the setting.
/// </summary>
/// <param name="settings">The settings.</param>
public override void UpdateSetting(MosaSettings settings)
{
//settings.LongExpansion = true; // required for ARM
}

/// <summary>
/// Gets the opcode encoder.
/// </summary>
public override OpcodeEncoder GetOpcodeEncoder()
{
return new OpcodeEncoder(32);
Expand Down Expand Up @@ -192,28 +199,19 @@ public override void InsertMoveInstruction(Context context, Operand destination,

if (destination.IsR4)
{
instruction = ARM32.Mvf;
instruction = ARM32.VMov;
}
else if (destination.IsR8)
{
instruction = ARM32.Mvf;
instruction = ARM32.VMov;
}

context.AppendInstruction(instruction, destination, source);
}

public override void InsertStoreInstruction(Context context, Operand destination, Operand offset, Operand value)
{
var instruction = ARM32.Str32;

if (destination.IsR4)
{
instruction = ARM32.Stf;
}
else if (destination.IsR8)
{
instruction = ARM32.Stf;
}
var instruction = destination.IsFloatingPoint ? ARM32.VStr : ARM32.Str32;

context.AppendInstruction(instruction, null, destination, offset, value);
}
Expand All @@ -228,16 +226,7 @@ public override void InsertStoreInstruction(Context context, Operand destination
/// <exception cref="NotImplementCompilerException"></exception>
public override void InsertLoadInstruction(Context context, Operand destination, Operand source, Operand offset)
{
var instruction = ARM32.Ldr32;

if (destination.IsR4)
{
instruction = ARM32.Ldf;
}
else if (destination.IsR8)
{
instruction = ARM32.Ldf;
}
var instruction = destination.IsFloatingPoint ? ARM32.VLdr : ARM32.Ldr32;

context.AppendInstruction(instruction, destination, source, offset);
}
Expand Down Expand Up @@ -271,7 +260,7 @@ public override void InsertJumpInstruction(Context context, BasicBlock destinati
/// <returns></returns>
public override bool IsInstructionMove(BaseInstruction instruction)
{
return instruction == ARM32.Mov || instruction == ARM32.Mvf;
return instruction == ARM32.Mov || instruction == ARM32.VMov;
}

/// <summary>
Expand Down
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