targets: configure L2 line size (#2647)

m-labs · Jan 16, 2025 · 2b48822 · 2b48822
1 parent 8ce6048
commit 2b48822
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Showing 3 changed files with 7 additions and 0 deletions.
diff --git a/artiq/gateware/targets/efc.py b/artiq/gateware/targets/efc.py
@@ -36,6 +36,7 @@ def __init__(self, gateware_identifier_str=None, hw_rev="v1.1", **kwargs):
                  cpu_bus_width=64,
                  sdram_controller_type="minicon",
                  l2_size=128*1024,
+                 l2_line_size=64,
                  clk_freq=125e6,
                  **kwargs)
         AMPSoC.__init__(self)

diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py
@@ -68,6 +68,7 @@ def __init__(self, gateware_identifier_str=None, with_wrpll=False, hw_rev="v2.0"
                          cpu_bus_width=cpu_bus_width,
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
+                         l2_line_size=64,
                          integrated_sram_size=8192,
                          ethmac_nrxslots=4,
                          ethmac_ntxslots=4,
@@ -176,6 +177,7 @@ def __init__(self, rtio_clk_freq=125e6, enable_sata=False, with_wrpll=False, gat
                          cpu_bus_width=cpu_bus_width,
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
+                         l2_line_size=64,
                          integrated_sram_size=8192,
                          ethmac_nrxslots=4,
                          ethmac_ntxslots=4,
@@ -427,6 +429,7 @@ def __init__(self, rtio_clk_freq=125e6, enable_sata=False, with_wrpll=False, *,
                  cpu_bus_width=cpu_bus_width,
                  sdram_controller_type="minicon",
                  l2_size=128*1024,
+                 l2_line_size=64,
                  clk_freq=rtio_clk_freq,
                  rtio_sys_merge=True,
                  **kwargs)

diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py
@@ -90,6 +90,7 @@ def __init__(self, gateware_identifier_str=None, drtio_100mhz=False, **kwargs):
                          cpu_bus_width=64,
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
+                         l2_line_size=64,
                          integrated_sram_size=8192,
                          ethmac_nrxslots=4,
                          ethmac_ntxslots=4,
@@ -187,6 +188,7 @@ def __init__(self, gateware_identifier_str=None, drtio_100mhz=False, **kwargs):
                          cpu_bus_width=64,
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
+                         l2_line_size=64,
                          integrated_sram_size=8192,
                          ethmac_nrxslots=4,
                          ethmac_ntxslots=4,
@@ -335,6 +337,7 @@ def __init__(self, gateware_identifier_str=None, sma_as_sat=False, drtio_100mhz=
                  cpu_bus_width=64,
                  sdram_controller_type="minicon",
                  l2_size=128*1024,
+                 l2_line_size=64,
                  integrated_sram_size=8192,
                  clk_freq=clk_freq,
                  rtio_sys_merge=True,