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Change 2-FIFOs to Pipes #668

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Change 2-FIFOs to Pipes #668

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e949f99
Change 2-FIFOs to Pipes
tilk Apr 18, 2024
f9b8f97
Change fifo_fetch
tilk Apr 18, 2024
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15 changes: 8 additions & 7 deletions coreblocks/core.py
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Original file line number Diff line number Diff line change
@@ -1,12 +1,13 @@
from amaranth import *
from amaranth.lib.wiring import flipped, connect
from transactron.lib.connectors import Pipe

from transactron.utils.dependencies import DependencyManager, DependencyContext
from coreblocks.func_blocks.interface.func_blocks_unifier import FuncBlocksUnifier
from coreblocks.priv.traps.instr_counter import CoreInstructionCounter
from coreblocks.priv.traps.interrupt_controller import InterruptController
from transactron.core import Transaction, TModule
from transactron.lib import FIFO, ConnectTrans
from transactron.lib import ConnectTrans
from coreblocks.interface.layouts import *
from coreblocks.interface.keys import (
BranchVerifyKey,
Expand Down Expand Up @@ -57,13 +58,13 @@ def __init__(self, *, gen_params: GenParams, wb_instr_bus: WishboneInterface, wb
self.core_counter = CoreInstructionCounter(self.gen_params)

# make fetch_continue visible outside the core for injecting instructions
self.fifo_fetch = FIFO(self.gen_params.get(FetchLayouts).raw_instr, 2)
self.pipe_fetch = Pipe(self.gen_params.get(FetchLayouts).raw_instr)

drop_args_transform = (self.gen_params.get(FetchLayouts).raw_instr, lambda _a, _b: {})
self.core_counter_increment_discard_map = MethodMap(
self.core_counter.increment, i_transform=drop_args_transform
)
self.fetch_continue = MethodProduct([self.fifo_fetch.write, self.core_counter_increment_discard_map.method])
self.fetch_continue = MethodProduct([self.pipe_fetch.write, self.core_counter_increment_discard_map.method])

self.free_rf_fifo = BasicFifo(
self.gen_params.get(SchedulerLayouts).free_rf_layout, 2**self.gen_params.phys_regs_bits
Expand Down Expand Up @@ -136,17 +137,17 @@ def elaborate(self, platform):

m.submodules.fetch_continue = self.fetch_continue
m.submodules.fetch = self.fetch
m.submodules.fifo_fetch = self.fifo_fetch
m.submodules.pipe_fetch = self.pipe_fetch
m.submodules.core_counter = self.core_counter
m.submodules.args_discard_map = self.core_counter_increment_discard_map

m.submodules.fifo_decode = fifo_decode = FIFO(self.gen_params.get(DecodeLayouts).decoded_instr, 2)
m.submodules.pipe_decode = pipe_decode = Pipe(self.gen_params.get(DecodeLayouts).decoded_instr)
m.submodules.decode = DecodeStage(
gen_params=self.gen_params, get_raw=self.fifo_fetch.read, push_decoded=fifo_decode.write
gen_params=self.gen_params, get_raw=self.pipe_fetch.read, push_decoded=pipe_decode.write
)

m.submodules.scheduler = Scheduler(
get_instr=fifo_decode.read,
get_instr=pipe_decode.read,
get_free_reg=free_rf_fifo.read,
rat_rename=frat.rename,
rob_put=rob.put,
Expand Down
9 changes: 4 additions & 5 deletions coreblocks/scheduler/scheduler.py
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Original file line number Diff line number Diff line change
Expand Up @@ -3,11 +3,10 @@
from amaranth import *

from transactron import Method, Transaction, TModule
from transactron.lib import FIFO
from coreblocks.interface.layouts import SchedulerLayouts
from coreblocks.params import GenParams
from coreblocks.frontend.decoder.optypes import OpType
from transactron.lib.connectors import Connect
from transactron.lib.connectors import Connect, Pipe
from transactron.utils import assign, AssignType
from transactron.utils.dependencies import DependencyManager
from coreblocks.interface.keys import CoreStateKey
Expand Down Expand Up @@ -399,7 +398,7 @@ def __init__(
def elaborate(self, platform):
m = TModule()

m.submodules.alloc_rename_buf = alloc_rename_buf = FIFO(self.layouts.reg_alloc_out, 2)
m.submodules.alloc_rename_buf = alloc_rename_buf = Pipe(self.layouts.reg_alloc_out)
m.submodules.reg_alloc = RegAllocation(
get_instr=self.get_instr,
push_instr=alloc_rename_buf.write,
Expand All @@ -415,15 +414,15 @@ def elaborate(self, platform):
gen_params=self.gen_params,
)

m.submodules.reg_alloc_out_buf = reg_alloc_out_buf = FIFO(self.layouts.rob_allocate_out, 2)
m.submodules.reg_alloc_out_buf = reg_alloc_out_buf = Pipe(self.layouts.rob_allocate_out)
m.submodules.rob_alloc = ROBAllocation(
get_instr=rename_out_buf.read,
push_instr=reg_alloc_out_buf.write,
rob_put=self.rob_put,
gen_params=self.gen_params,
)

m.submodules.rs_select_out_buf = rs_select_out_buf = FIFO(self.layouts.rs_select_out, 2)
m.submodules.rs_select_out_buf = rs_select_out_buf = Pipe(self.layouts.rs_select_out)
m.submodules.rs_selector = RSSelection(
gen_params=self.gen_params,
get_instr=reg_alloc_out_buf.read,
Expand Down