arm: Add ISB before WFI, after enabling timer

When booting secondary CPU cores, Fiasco currently enables timer
interrupts shortly followed by going idle using WFI (see
app_cpu_thread.cpp). Without an instruction barrier (ISB), the sequence
of

  Timer_tick::enable(ccpu);
  ...
  Proc::halt();

or more precisely on Arm64

  msr CNTHP_CTL_EL2, ...
  ...
  wfi

does not guarantee that the timer actually got enabled before the WFI
gets executed. The CPU can execute the WFI out of order before
completing MSR.  In this case, secondary CPU cores do not receive any
timer interrupts before they are woken up by other means, e.g. the
kernel debugger.

Fix this by adding an explicit ISB before WFI, similar to the already
existing DSB.

Change-Id: Ic879ce9ffcf07c6852d1b062b8b09eb06990db76

src/lib/libk/arm/processor-arm.cpp

@@ -228,6 +228,7 @@ void Proc::halt()
 {
   Status f = cli_save();
   asm volatile("dsb sy \n\t"
+               "isb sy \n\t"
                "wfi \n\t");
   sti_restore(f);
 }