riscv: Fix build error due to missing Hedeleg_mask

In `cpu_virt && !fpu` configurations the constant Hedeleg_mask was not
defined.

Change-Id: Idb18c57db1b7758071dc2f528db31b25a3eba121

src/kern/riscv/cpu-riscv-hyp.cpp

@@ -92,33 +92,14 @@ class Cpu
     /// Hstatus bits that are set for user mode context by default.
     Hstatus_user_default = 0,
   };
-};
-
-//----------------------------------------------------------------------------
-INTERFACE [riscv && cpu_virt && fpu && lazy_fpu]:
-
-EXTENSION
-class Cpu
-{
-public:
-  enum : Mword
-  {
-    // Cannot delegate illegal instruction exception as we need it for lazy FPU
-    // switching.
-    Hedeleg_mask = ~(1UL << Exc_illegal_inst),
-  };
-};
-
-//----------------------------------------------------------------------------
-INTERFACE [riscv && cpu_virt && fpu && !lazy_fpu]:
 
-EXTENSION
-class Cpu
-{
-public:
   enum : Mword
   {
-    Hedeleg_mask = ~0UL,
+    // With lazy FPU switching we cannot delegate illegal instruction exception,
+    // as we need it to detect usage of disabled FPU, i.e. the case that
+    // currently someone else is the FPU owner.
+    Hedeleg_mask = TAG_ENABLED(fpu && lazy_fpu)
+                   ? ~(1UL << Exc_illegal_inst) : ~0UL,
   };
 };