map hdae5000 ROM & RAM to maincpu memory map

I am still not sure how to map the rest of i/o And I am getting a segfault when I load the driver without attaching the extension board, so I am probably doing it wrong here.
felipesanches · Jan 2, 2024 · fffecba · fffecba
1 parent a2a1986
commit fffecba
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Showing 2 changed files with 24 additions and 7 deletions.
diff --git a/src/devices/bus/technics/hdae5000.cpp b/src/devices/bus/technics/hdae5000.cpp
@@ -61,20 +61,18 @@ ROM_START(hdae5000)
 ROM_END
 
 void hdae5000_device::rom_map(address_map &map)
+{
+	map(0x00000, 0x7ffff).rom().region(m_rom, 0);
+}
+
+void hdae5000_device::io_map(address_map &map)
 {
 	//map(0x130000, 0x13ffff).m(m_hddc, FUNC(?_device::?)); // Hard-drive Controller (model?) IC? on HD-AE5000 board 
 	//map(0x160000, 0x16ffff) ... Optional parallel port interface (NEC uPD71055) IC9
 	map(0x160000, 0x160000).lrw8([this](offs_t a) { return m_ppi->read(0); }, "ppi_r0", [this](offs_t a, u8 data) { m_ppi->write(0, data); }, "ppi_w0");
 	map(0x160002, 0x160002).lrw8([this](offs_t a) { return m_ppi->read(1); }, "ppi_r1", [this](offs_t a, u8 data) { m_ppi->write(1, data); }, "ppi_w1");
 	map(0x160004, 0x160004).lrw8([this](offs_t a) { return m_ppi->read(2); }, "ppi_r2", [this](offs_t a, u8 data) { m_ppi->write(2, data); }, "ppi_w2");
 	map(0x160006, 0x160006).lrw8([this](offs_t a) { return m_ppi->read(3); }, "ppi_r3", [this](offs_t a, u8 data) { m_ppi->write(3, data); }, "ppi_w3");
-	map(0x200000, 0x27ffff).ram(); //optional hsram: 2 * 256k bytes Static RAM @ IC5, IC6 (CS5)
-	map(0x280000, 0x2fffff).rom().region(m_rom, 0); // 512k bytes FLASH ROM @ IC4 (CS5)
-	map(0x800000, 0x8fffff).ram(); // hack <- I think this is the SRAM from the HD-AE5000 board
-}
-
-void hdae5000_device::io_map(address_map &map)
-{
 }
 
 const tiny_rom_entry *hdae5000_device::device_rom_region() const

diff --git a/src/mame/technics/kn5000.cpp b/src/mame/technics/kn5000.cpp
@@ -30,6 +30,7 @@ class kn5000_state : public driver_device
 		, m_fdc(*this, "fdc")
 		, m_checking_device_led_cn11(*this, "checking_device_led_cn11")
 		, m_extension(*this, "extension")
+		, m_extension_view(*this, "extension_view")
 	{ }
 
 	void kn5000(machine_config &config);
@@ -40,7 +41,9 @@ class kn5000_state : public driver_device
 	required_device<upd72067_device> m_fdc;
 	required_device<beep_device> m_checking_device_led_cn11;
 	required_device<kn5000_extension_device> m_extension;
+	memory_view m_extension_view;
 
+	virtual void machine_start() override;
 	virtual void machine_reset() override;
 
 //	void maincpu_portb_w(offs_t offset, uint8_t data);
@@ -76,6 +79,9 @@ void kn5000_state::maincpu_mem(address_map &map)
 	map(0x1703b0, 0x1703df).m("vga", FUNC(vga_device::io_map)); // LCD controller @ IC206
 	map(0x1a0000, 0x1bffff).rw("vga", FUNC(vga_device::mem_linear_r), FUNC(vga_device::mem_linear_w));
 	map(0x1e0000, 0x1fffff).ram(); // 1Mbit SRAM @ IC21 (CS0)  Note: I think this is the message "ERROR in back-up SRAM"
+	map(0x200000, 0x2fffff).view(m_extension_view);
+	m_extension_view[0](0x200000, 0x27ffff).ram(); //optional hsram: 2 * 256k bytes Static RAM @ IC5, IC6 (CS5)
+	m_extension_view[0](0x280000, 0x2fffff).rom(); // 512k bytes FLASH ROM @ IC4 (CS5)
 	map(0x300000, 0x3fffff).rom().region("custom_data", 0); // 8MBit FLASH ROM @ IC19 (CS5)
 	map(0x400000, 0x7fffff).rom().region("rhythm_data", 0); // 32MBit ROM @ IC14 (A22=1 and CS5)
 	map(0xc00000, 0xdfffff).mirror(0x200000).rom().region("table_data", 0);//2 * 8MBit ROMs @ IC1, IC3 (CS2)
@@ -141,6 +147,19 @@ INPUT_PORTS_END
 //	// TODO: Implement-me!
 //}
 
+void kn5000_state::machine_start()
+{
+	if(m_extension)
+	{
+		m_extension->rom_map(m_extension_view[0], 0x280000, 0x2fffff);
+		m_extension_view.select(0);
+	}
+	else
+	{
+		m_extension_view.disable();
+	}
+}
+
 void kn5000_state::machine_reset()
 {
 	/* Setup beep */