remove(beta_targets): Removed support for beta chip targets

BREAKING CHANGE

.gitlab-ci.yml

@@ -110,15 +110,12 @@ host_tests_espefuse:
         - esp32c2
         - esp32c3
         - esp32c5
-        - esp32c5beta3
         - esp32c6
         - esp32c61
         - esp32h2
-        - esp32h2beta1
         - esp32p4
         - esp32s2
         - esp32s3
-        - esp32s3beta2
         - esp32h21
   script:
     - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip ${TARGET}

ci/download_flasher_stubs.py

@@ -1,6 +1,6 @@
 #!/usr/bin/env python
 #
-# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 import glob
@@ -18,17 +18,12 @@
             "esp32c2",
             "esp32c3",
             "esp32c5",
-            "esp32c5beta3",
             "esp32c6",
             "esp32c61",
-            "esp32c6beta",
             "esp32h2",
-            "esp32h2beta1",
-            "esp32h2beta2",
             "esp32p4",
             "esp32s2",
             "esp32s3",
-            "esp32s3beta2",
             "esp8266",
         ),
         "LICENSE": "released as Free Software under GNU General Public License Version 2 or later",

docs/en/migration-guide.rst

@@ -13,14 +13,14 @@ The output format of the :ref:`image_info <image-info>` command has been **updat
 
 **Changes in the New Format:**
 
-- Improved readability and structure
-- Additional metadata fields for better debugging and analysis
-- Consistent formatting for all ESP chip variants
+- Improved readability and structure.
+- Additional metadata fields for better debugging and analysis.
+- Consistent formatting for all ESP chip variants.
 
 **Migration Steps:**
 
-1. Update any scripts or tools that parse the ``image_info`` output to use the new format
-2. Remove any ``--version`` arguments from ``image_info`` commands
+1. Update any scripts or tools that parse the ``image_info`` output to use the new format.
+2. Remove any ``--version`` arguments from ``image_info`` commands.
 
 Output Logging
 **************
@@ -73,3 +73,21 @@ In ``v5``, error handling and output behavior have been improved to provide bett
 
 1. Update scripts that rely on parsing STDOUT for error messages to check STDERR instead.
 2. Ensure scripts handle non-zero exit codes correctly in the case of operations interrupted by the user.
+
+Beta Target Support Removal
+***************************
+
+Support for the following beta targets has been **removed in v5**:
+
+- ESP32-C5(beta3)
+- ESP32-C6(beta)
+- ESP32-H2(beta1)
+- ESP32-H2(beta2)
+- ESP32-S3(beta2)
+
+**Migration Steps:**
+
+1. Update any scripts or workflows not to target these beta chips.
+2. Remove any references to these beta targets from CI/CD pipelines or build scripts.
+
+Use esptool ``v4`` for legacy workflows targeting these beta chips.

espefuse/__init__.py

@@ -1,4 +1,4 @@
-# SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2016-2025 Espressif Systems (Shanghai) CO LTD
 #
 # SPDX-License-Identifier: GPL-2.0-or-later
 # PYTHON_ARGCOMPLETE_OK
@@ -13,16 +13,13 @@
 import espefuse.efuse.esp32c2 as esp32c2_efuse
 import espefuse.efuse.esp32c3 as esp32c3_efuse
 import espefuse.efuse.esp32c5 as esp32c5_efuse
-import espefuse.efuse.esp32c5beta3 as esp32c5beta3_efuse
 import espefuse.efuse.esp32c6 as esp32c6_efuse
 import espefuse.efuse.esp32c61 as esp32c61_efuse
 import espefuse.efuse.esp32h2 as esp32h2_efuse
 import espefuse.efuse.esp32h21 as esp32h21_efuse
-import espefuse.efuse.esp32h2beta1 as esp32h2beta1_efuse
 import espefuse.efuse.esp32p4 as esp32p4_efuse
 import espefuse.efuse.esp32s2 as esp32s2_efuse
 import espefuse.efuse.esp32s3 as esp32s3_efuse
-import espefuse.efuse.esp32s3beta2 as esp32s3beta2_efuse
 
 import esptool
 from esptool.logger import log
@@ -59,20 +56,11 @@
     "esp32c6": DefChip("ESP32-C6", esp32c6_efuse, esptool.targets.ESP32C6ROM),
     "esp32c61": DefChip("ESP32-C61", esp32c61_efuse, esptool.targets.ESP32C61ROM),
     "esp32c5": DefChip("ESP32-C5", esp32c5_efuse, esptool.targets.ESP32C5ROM),
-    "esp32c5beta3": DefChip(
-        "ESP32-C5(beta3)", esp32c5beta3_efuse, esptool.targets.ESP32C5BETA3ROM
-    ),
     "esp32h2": DefChip("ESP32-H2", esp32h2_efuse, esptool.targets.ESP32H2ROM),
     "esp32h21": DefChip("ESP32-H21", esp32h21_efuse, esptool.targets.ESP32H21ROM),
     "esp32p4": DefChip("ESP32-P4", esp32p4_efuse, esptool.targets.ESP32P4ROM),
-    "esp32h2beta1": DefChip(
-        "ESP32-H2(beta1)", esp32h2beta1_efuse, esptool.targets.ESP32H2BETA1ROM
-    ),
     "esp32s2": DefChip("ESP32-S2", esp32s2_efuse, esptool.targets.ESP32S2ROM),
     "esp32s3": DefChip("ESP32-S3", esp32s3_efuse, esptool.targets.ESP32S3ROM),
-    "esp32s3beta2": DefChip(
-        "ESP32-S3(beta2)", esp32s3beta2_efuse, esptool.targets.ESP32S3BETA2ROM
-    ),
 }