Initial MIPS CPUs support #1990
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For Python CI test I'm not sure what's the best way to provide source to CI action, probably create pythondata package for both? |
This was referenced Jun 18, 2024
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Thanks for adding this! |
For MIPS CPUs, there is a default memory translation (which VA = PA + offset). BIOS needs to access memory with translated virtual address. Add bios_map hook and generated various address macros with _VA suffix to allow BIOS to use virtual addresses. It is defaulted to 1:1 mapping so it won't affect other CPUs. Signed-off-by: Jiaxun Yang <[email protected]>
Use addresses with _VA suffix for memory and registers accress. Signed-off-by: Jiaxun Yang <[email protected]>
MIPS toolchains are always capable for compiling to both endian and bitness targets, so define a single CPU_GCC_TRIPLE_MIPS to cover them all. Signed-off-by: Jiaxun Yang <[email protected]>
Signed-off-by: Jiaxun Yang <[email protected]>
CQU Dual Issue Machine, Dual issue 5-stage pipeline MIPS32 CPU capable for running Linux. https://github.com/Maxpicca-Li/CDIM Signed-off-by: Jiaxun Yang <[email protected]>
Loongson GS232 Dual issue pipeline MIPS32 CPU capable for running Linux. Opensourced by Loongson under 2-Clause BSD License (as shown in verilog source). Signed-off-by: Jiaxun Yang <[email protected]>
intel-lab-lkp
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Jul 6, 2024
The LiteX framework provides a convenient and efficient infrastructure to create FPGA Cores/SoCs. We have implemented LiteX support for a couple of opensource MIPS CPU cores including microAptiv UP from MIPS, GS232 from Loongson, and CDIM from CQU. For this platform, devicetree is generated by litex python scripts so there is no devicetree addition necessary. Link: enjoy-digital/litex#1990 Signed-off-by: Jiaxun Yang <[email protected]>
intel-lab-lkp
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Jul 14, 2024
The LiteX framework provides a convenient and efficient infrastructure to create FPGA Cores/SoCs. We have implemented LiteX support for a couple of opensource MIPS CPU cores including microAptiv UP from MIPS, GS232 from Loongson, and CDIM from CQU. For this platform, devicetree is generated by litex python scripts so there is no devicetree addition necessary. Link: enjoy-digital/litex#1990 Signed-off-by: Jiaxun Yang <[email protected]>
staging-kernelci-org
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Jul 16, 2024
The LiteX framework provides a convenient and efficient infrastructure to create FPGA Cores/SoCs. We have implemented LiteX support for a couple of opensource MIPS CPU cores including microAptiv UP from MIPS, GS232 from Loongson, and CDIM from CQU. For this platform, devicetree is generated by litex python scripts so there is no devicetree addition necessary. Link: enjoy-digital/litex#1990 Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
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@enjoy-digital Any comments? |
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@FlyGoat: Sorry, I've been very busy recently. I'll have a closer look in late August/early September. |
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Hi @FlyGoat , Sorry for running into your issue thread all of a sudden. I am wondering if the CDIM (and other MIPS CPUS lised here) are landing to LiteX-hubs ? If not, would you be so kind to provide some info so bystanders folks like me could lay hands on them ? Cordially yours, |
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Hi @Ruinland, I think it's pending on this PR? Thanks! |
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Hi @enjoy-digital apologies for chasing on this, another gentle ping :-) |
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Hi,
This PR implemented initial support for MIPS based CPUs, it implemented
bios_maphook for CPU to deal with problem mentioned in #1903, fixed AHB bus handling then added two CPUs as examples.Please review.
Thanks