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litex/soc/cores/cpu/__init__, litex/soc/integration/soc: modifying CPUNone to adapt data_width and io_regions according to bus data_width/address_width #1823

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Oct 30, 2023
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litex/soc/cores/cpu/__init__, litex/soc/integration/soc: modifying CPUNone to adapt data_width and io_regions according to bus data_width/address_width #1823

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6 changes: 4 additions & 2 deletions litex/soc/cores/cpu/__init__.py
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Original file line number Diff line number Diff line change
Expand Up @@ -50,11 +50,9 @@ def disable_reset_address_check(self):

class CPUNone(CPU):
variants = ["standard"]
data_width = 32
endianness = "little"
reset_address = 0x00000000
reset_address_check = False
io_regions = {0x0000_0000: 0x1_0000_0000} # origin, length
periph_buses = []
memory_buses = []
mem_map = {
Expand All @@ -63,6 +61,10 @@ class CPUNone(CPU):
"spiflash" : 0x1000_0000, # FIXME: Remove.
}

def __init__(self, data_width=32, addr_width=32):
self.io_regions = {0: int(2**float(addr_width))} # origin, length
self.data_width = data_width

# CPUs GCC Triples ---------------------------------------------------------------------------------

CPU_GCC_TRIPLE_RISCV64 = (
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5 changes: 4 additions & 1 deletion litex/soc/integration/soc.py
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Original file line number Diff line number Diff line change
Expand Up @@ -1082,7 +1082,10 @@ def add_cpu(self, name="vexriscv", variant="standard", reset_address=None, cfu=N
colorer("\n - ".join(sorted(cpu_cls.variants)))))
raise SoCError()
self.check_if_exists("cpu")
self.cpu = cpu_cls(self.platform, variant)
if cpu_cls is cpu.CPUNone:
self.cpu = cpu_cls(self.bus.data_width, self.bus.address_width)
else:
self.cpu = cpu_cls(self.platform, variant)
self.logger.info("CPU {} {}.".format(
colorer(name, color="underline"),
colorer("added", color="green")))
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