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Add wishbone word/byte addressing.#1817

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enjoy-digital merged 9 commits intomasterenjoy-digital/litex:masterfrom wishbone_word_byte_addressingenjoy-digital/litex:wishbone_word_byte_addressingCopy head branch name to clipboardOct 27, 2023

+192-104

Commits

Commits on Oct 26, 2023

• interconnect/wishbone: Add addressing parameter/property to allow Wishbone to use byte addressing (Currently using word addressing).

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• axi/axi_full: Add addressing parameters and assert on byte.

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• axi/axi_lite: Add addressing parameters and assert on byte.

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• ahb: Add addressing property and different address shift in AHB2Wishbone when Wishbone is byte/word addressed.

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• csr_bus: Add addressing property.

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• axi/axi_lite_to_wishbone: Add different address shift when Wishbone is byte/word addressed.

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• soc/add_adapter: Add initial addressing conversion between byte/word addressed.

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• cores/cpu: Make data_width/address_width/addressing explicit for all Wishbone interfaces.

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• cores/cpu: Switch Wishbone interfaces to byte addressing where possible and remove address shifting.

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