cores/video/VideoFramebuffer: Skip first frame on enable to ensure pr…

…oper VTG/DMA synchronization.
enjoy-digital · Nov 5, 2023 · b0c0669 · b0c0669
1 parent f4e68d7
commit b0c0669
Showing 1 changed file with 11 additions and 2 deletions.
diff --git a/litex/soc/cores/video.py b/litex/soc/cores/video.py
@@ -693,13 +693,18 @@ def __init__(self, dram_port, hres=800, vres=600, base=0x00000000, fifo_depth=65
             video_pipe_source = self.cdc.source
 
         # Video Synchronization/Generation.
+        first = Signal()
         fsm = FSM(reset_state="SYNC")
         fsm = ClockDomainsRenamer(clock_domain)(fsm)
         fsm = ResetInserter()(fsm)
         self.submodules += fsm
         self.specials += MultiReg(self.dma.fsm.reset, fsm.reset, clock_domain)
         fsm.act("SYNC",
-            vtg_sink.ready.eq(~fsm.reset),
+            vtg_sink.ready.eq(1),
+            If(fsm.reset,
+                vtg_sink.ready.eq(0),
+                NextValue(first, 1)
+            ),
             If(vtg_sink.valid & vtg_sink.last,
                 NextState("RUN")
             ),
@@ -709,9 +714,13 @@ def __init__(self, dram_port, hres=800, vres=600, base=0x00000000, fifo_depth=65
             vtg_sink.ready.eq(1),
             If(vtg_sink.valid & vtg_sink.de,
                 video_pipe_source.connect(source, keep={"valid", "ready"}),
+                If(first,
+                    source.valid.eq(0)
+                ),
                 vtg_sink.ready.eq(source.valid & source.ready),
                 If(video_pipe_source.valid & video_pipe_source.last,
-                    NextState("SYNC")
+                    NextValue(first, 0),
+                    NextState("SYNC"),
                 )
             ),
             vtg_sink.connect(source, keep={"de", "hsync", "vsync"}),