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updated caseDicts to work with ospx 'refactor' branch.
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Claas committed May 25, 2022
1 parent dae2156 commit fb3ddbb
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Showing 3 changed files with 189 additions and 98 deletions.
25 changes: 25 additions & 0 deletions demo commands summary.txt
Original file line number Diff line number Diff line change
@@ -0,0 +1,25 @@
cd farn-demo
ae
cd farn
farn farnDict --sample
farn sampled.farnDict --generate
farn sampled.farnDict --execute copy
farn sampled.farnDict --execute parse
farn sampled.farnDict --execute build
farn sampled.farnDict --execute run -q
farn sampled.farnDict --execute post
./resetDemo.bat

cd ospCaseBuilder
ospCaseBuilder --inspect caseDict --verbose --log inspect.log --log-level INFO
ospCaseBuilder caseDict --graph
ospCaseBuilder caseDict
cosim run OspSystemStructure.xml -b 0 -d 10 --real-time --log-level debug
watchCosim watchDict -pd
./resetDemo.bat

cd importSystemStructure
cd template
importSystemStructure ..\house\OspSystemStructure.xml
cd ..
./resetDemo.bat
131 changes: 82 additions & 49 deletions farn/template/caseDict
Original file line number Diff line number Diff line change
Expand Up @@ -14,23 +14,55 @@ systemStructure
{
minuend_to_difference
{
source minuend_output_port;
target difference_minuend_input_port;
source
{
component minuend;
connector minuend_output;
}
target
{
component difference;
connector difference_input_minuend;
}
}
subtrahend_to_difference
{
source subtrahend_output_port;
target difference_subtrahend_input_port;
source
{
component subtrahend;
connector subtrahend_output;
}
target
{
component difference;
connector difference_input_subtrahend;
}
}
dividend_to_quotient
{
source dividend_output_port;
target quotient_dividend_input_port;
source
{
component dividend;
connector dividend_output;
}
target
{
component quotient;
connector quotient_input_dividend;
}
}
difference_to_divisor
{
source difference_output_port;
target quotient_divisor_input_port;
source
{
component difference;
connector difference_output;
}
target
{
component quotient;
connector quotient_input_divisor;
}
}
}
components
Expand All @@ -39,109 +71,109 @@ systemStructure
{
connectors
{
difference_minuend_input_port
difference_input_minuend
{
reference difference.IN1;
type input;
variable difference.IN1;
type input;
}
difference_subtrahend_input_port
difference_input_subtrahend
{
reference difference.IN2;
type input;
variable difference.IN2;
type input;
}
difference_output_port
difference_output
{
reference difference.OUT;
type input;
variable difference.OUT;
type output;
}
}
fmu difference.fmu;
fmu difference.fmu;
}
quotient
{
connectors
{
quotient_dividend_input_port
quotient_input_dividend
{
reference quotient.IN1;
type input;
variable quotient.IN1;
type input;
}
quotient_divisor_input_port
quotient_input_divisor
{
reference quotient.IN2;
type input;
variable quotient.IN2;
type input;
}
quotient_output_port
quotient_output
{
reference quotient.OUT;
type input;
variable quotient.OUT;
type output;
}

}
fmu quotient.fmu;
fmu quotient.fmu;
}
minuend
{
connectors
{
minuend_output_port
minuend_output
{
reference constVal.OUT;
type output;
variable constVal.OUT;
type output;
}
}
initialize
{
constVal.IN
{
causality parameter;
start $minuend;
variability fixed;
causality parameter;
variability fixed;
start $minuend;
}
}
fmu constantVal.fmu;
fmu constantVal.fmu;
}
subtrahend
{
connectors
{
subtrahend_output_port
subtrahend_output
{
reference constVal.OUT;
type output;
variable constVal.OUT;
type output;
}
}
initialize
{
constVal.IN
{
causality parameter;
start $subtrahend;
variability fixed;
causality parameter;
variability fixed;
start $subtrahend;
}
}
fmu constantVal.fmu;
fmu constantVal.fmu;
}
dividend
{
connectors
{
dividend_output_port
dividend_output
{
reference constVal.OUT;
type output;
variable constVal.OUT;
type output;
}
}
initialize
{
constVal.IN
{
causality parameter;
start $dividend;
variability fixed;
causality parameter;
variability fixed;
start $dividend;
}
}
fmu constantVal.fmu;
fmu constantVal.fmu;
}
}
}
Expand All @@ -153,5 +185,6 @@ run
startTime 0;
stopTime 10;
baseStepSize 0.01;
algorithm fixedStep;
}
}
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