agenda: update for index 152

Signed-off-by: Ryan Tsien <[email protected]>
cnrv · Aug 9, 2024 · 137e7a1 · 137e7a1
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diff --git a/content/en/agenda.md b/content/en/agenda.md
@@ -735,12 +735,12 @@ a23_A:
     authors:
       - name: 杜超
         title: 北京奕斯伟计算技术股份有限公司，智能计算事业部-云组件开发部部长
-  - title: leverage BRS (Boot and runtime service) relevant standards to improve RISC-V SW compatibility
+  - title: Leverage BRS standard to improve RISC-V SW compatibility
     time: 17:30
     duration: 10
     index: 152
     authors:
-      - name: 许海波
+      - name: Haibo Xu
         title: Intel, RISC-V Software Engineer
       - name: Andrei Warkentin
         title: Intel, Principal Engineer

diff --git a/content/zh/agenda.md b/content/zh/agenda.md
@@ -735,7 +735,7 @@ a23_A:
     authors:
       - name: 杜超
         title: 北京奕斯伟计算技术股份有限公司，智能计算事业部-云组件开发部部长
-  - title: leverage BRS (Boot and runtime service) relevant standards to improve RISC-V SW compatibility
+  - title: Leverage BRS standard to improve RISC-V SW compatibility
     time: 17:30
     duration: 10
     index: 152