v0.6.22
- Fixes bugs:
- Bug in DEC transformation overwrites case-alternatives
- Bug in DEC transformation creates non-representable let-binders
- VHDL: Incorrect primitive for
Integer
sltInteger#
andgeInteger#
- (System)Verilog: Fix primitive for CLaSH.Sized.Internal.Signed.mod# and GHC.Type.Integer.modInteger #164