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v0.6.22

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@christiaanb christiaanb released this 03 Aug 09:02
· 4545 commits to master since this release
  • Fixes bugs:
    • Bug in DEC transformation overwrites case-alternatives
    • Bug in DEC transformation creates non-representable let-binders
    • VHDL: Incorrect primitive for Integers ltInteger# and geInteger#
    • (System)Verilog: Fix primitive for CLaSH.Sized.Internal.Signed.mod# and GHC.Type.Integer.modInteger #164