v0.5.9

• New features:
  • Use new verilog backend which outputs Verilog-2001 instead of Verilog-2005: generated Verilog is now accepted by Altera/Quartus
• Fixes bugs:
  • --systemverilog switch incorrectly generates verilog code instead of systemverilog code
  • Incorrect SV primitive for CLaSH.Prelude.Testbench.assert'
  • Incorrect SV primitive for CLaSH.Sized.Vec.index_int
  • Sometimes created incorrect nested generate statements in SV backend