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Update CHANGELOG.md in preparation of 1.2.1
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martijnbastiaan committed Apr 23, 2020
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# Changelog for the Clash project

## 1.3.0
See `changelog/README.md`
## 1.2.1 *April 23rd 2020*
* Changed:
* Treat `Signed 0`, `Unsigned 0`, `Index 1`, `BitVector 0` as unit. In effect this means that 'minBound' and 'maxBound' return 0, whereas previously they might crash [#1183](https://github.com/clash-lang/clash-compiler/issues/1183)
* Infix use of `deepseqX` is now right-associative

* New features (API):
* Added basic support for writing PSL/SVA assertions in `Clash.Verification`
* New features (Compiler):
* No new features yet!
* Fixes issues:
* No fixes yet!
* Fixes without issue reports:
* Use `ByteArray` instead of `Vector Word8` in the `ByteArrayLiteral` type. See [#1151](https://github.com/clash-lang/clash-compiler/pull/1151)
* Added:
* Add 'natToInteger', 'natToNatural', and 'natToNum'. Similar to 'snatTo*', but works solely on a type argument instead of an SNat.
* `Clash.Sized.Vector.unfoldr` and `Clash.Sized.Vector.unfoldrI` to construct vectors from a seed value
* Added NFDataX instances for `Data.Monoid.{First,Last}`

* Fixed:
* The Verilog backend can now deal with non-contiguous ranges in custom bit-representations.
* Synthesizing BitPack instances for type with phantom parameter fails [#1242](https://github.com/clash-lang/clash-compiler/issues/1242)
* Synthesis of `fromBNat (toBNat d5)` failed due to `unsafeCoerce` coercing from `Any`
* Memory leak in register primitives [#1256](https://github.com/clash-lang/clash-compiler/issues/1256)
* Illegal VHDL slice when projecting nested SOP type [#1254](https://github.com/clash-lang/clash-compiler/issues/1254)
* Vivado VHDL code path (`-fclash-hdlsyn Vivado`) generates illegal VHDL [#1264](https://github.com/clash-lang/clash-compiler/issues/1264)

## 1.2.0 *March 5th 2020*
As promised when releasing 1.0, we've tried our best to keep the API stable. We
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