Merge remote-tracking branch 'origin/master' into 0.7

clash-ghc/CHANGELOG.md

@@ -1,12 +1,28 @@
 # Changelog for the [`clash-ghc`](http://hackage.haskell.org/package/clash-ghc) package
 
+##
+* New features:
+  * Support distribution of primitive templates with Cabal/Hackage packages [commit](https://github.com/clash-lang/clash-compiler/commit/82cd31863aafcbaf3bdbf7746d89d13859af5aaf)
+  * Find memory data files and primitive files relative to import dirs (`-i<DIR>`)
+  * Add 'clashi' program and 'clash-ghc' package [#208](https://github.com/clash-lang/clash-compiler/issues/208), thanks to @thoughtpolice
+* Fixes bugs:
+  * `case (EmptyCase ty) of ty' { ... }` -> `EmptyCase ty'` [#198](https://github.com/clash-lang/clash-compiler/issues/198)
+  * `BitVector.split#` apply the correct type arguments
+
 ## 0.7.0.1 *January 17th 2017
 * Fixes bugs:
   * Include HsVersions.h in source distribution
 
 ## 0.7 *January 16th 2017*
 * New features:
   * Support for `clash-prelude` 0.11
+  * Primitive templates can include QSys files
+  * VHDL blackboxes: support additional libraries and uses keywords in generated VHDL
+  * Highly limited Float/Double support (literals and `Rational` conversion), hidden behind the `-clash-float-support` flag.
+* Fixes bugs:
+  * Reduce type families inside clock period calculation [#180](https://github.com/clash-lang/clash-compiler/issues/180)
+  * Only output signed literals as hex when they're multiple of 4 bits [#187](https://github.com/clash-lang/clash-compiler/issues/187)
+  * Correctly print negative hex literals
 
 ## 0.6.24 *October 17th 20168
 * Call generatePrimMap after loadModules [#175](https://github.com/clash-lang/clash-compiler/pull/175)

clash-lib/CHANGELOG.md

@@ -1,8 +1,23 @@
 # Changelog for the [`clash-lib`](http://hackage.haskell.org/package/clash-lib) package
 
+##
+* New features:
+  * Support distribution of primitive templates with Cabal/Hackage packages [commit](https://github.com/clash-lang/clash-compiler/commit/82cd31863aafcbaf3bdbf7746d89d13859af5aaf)
+  * Find memory data files and primitive files relative to import dirs (`-i<DIR>`)
+* Fixes bugs:
+  * `case (EmptyCase ty) of ty' { ... }` -> `EmptyCase ty'` [#198](https://github.com/clash-lang/clash-compiler/issues/198)
+  * `BitVector.split#` apply the correct type arguments
+
 ## 0.7 *January 16th 2017*
 * New features:
   * Support for `clash-prelude` 0.11
+  * Primitive templates can include QSys files
+  * VHDL blackboxes: support additional libraries and uses keywords in generated VHDL
+  * Highly limited Float/Double support (literals and `Rational` conversion), hidden behind the `-clash-float-support` flag.
+* Fixes bugs:
+  * Reduce type families inside clock period calculation [#180](https://github.com/clash-lang/clash-compiler/issues/180)
+  * Only output signed literals as hex when they're multiple of 4 bits [#187](https://github.com/clash-lang/clash-compiler/issues/187)
+  * Correctly print negative hex literals
 
 ## 0.6.21 *August 18th 2016*
 * Fixes bugs:

clash-systemverilog/CHANGELOG.md

@@ -1,5 +1,13 @@
 # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package
 
+##
+* Fixes bugs:
+  * Incorrect unsigned->signed wrap-around and conversion
+  * Use unpacked array syntax in array literals
+  * Add braces when converting unpacked to packed arrays
+  * Fixed `rotateLeftS` systemverilog template
+  * Do not generate null-slices
+
 ## 0.7 *January 16th 2017*
 * New features:
   * Support `clash-prelude` 0.11

clash-systemverilog/src/CLaSH/Backend/SystemVerilog.hs

@@ -228,27 +228,41 @@ topSortHWTys hwtys = sorted
                              in concatMap (\(_,tys) -> mapMaybe (\ty -> liftM (ti,,()) (HashMap.lookup ty nodesI)) tys) ctys
     edge _                 = []
 
+range :: Either Int Int -> SystemVerilogM Doc
+range (Left n)  = brackets (int (n-1) <> colon <> int 0)
+range (Right n) = brackets (int 0 <> colon <> int (n-1))
+
 tyDec :: HWType -> SystemVerilogM (Maybe Doc)
 tyDec ty@(Vector n elTy) | typeSize ty > 0 = Just A.<$> do
   syn <- hdlSyn
   case syn of
-    Vivado -> "typedef" <+> "logic" <+> brackets (int (typeSize elTy - 1) <> colon <> int 0) <+>
-              tyName ty <+> brackets (int 0 <> colon <> int (n-1)) <> semi
-    _ -> do case splitVecTy ty of
-              Just (ns,elTy') -> do
-                let ranges = hcat (mapM (\n' -> brackets (int 0 <> colon <> int (n'-1))) (tail ns))
-                "typedef" <+> elTy' <+> ranges <+> tyName ty <+> brackets (int 0 <> colon <> int (head ns - 1)) <> semi
-              _ -> error $ $(curLoc) ++ "impossible"
+    Vivado -> case splitVecTy ty of
+      Just ([Right n',Left n''],elTy') ->
+        "typedef" <+> elTy' <+> brackets (int (n''-1) <> colon <> int 0) <+>
+        tyName ty <+> brackets (int 0 <> colon <> int (n'-1)) <> semi
+      _ ->
+        "typedef" <+> "logic" <+> brackets (int (typeSize elTy - 1) <> colon <> int 0) <+>
+        tyName ty <+> brackets (int 0 <> colon <> int (n-1)) <> semi
+    _ -> case splitVecTy ty of
+      Just (Right n':ns,elTy') ->
+        "typedef" <+> elTy' <+> hcat (mapM range ns) <+> tyName ty <+>
+        brackets (int 0 <> colon <> int (n' - 1)) <> semi
+      _ -> error $ $(curLoc) ++ "impossible"
 tyDec ty@(RTree n elTy) | typeSize elTy > 0 = Just A.<$> do
   syn <- hdlSyn
   case syn of
-    Vivado -> "typedef" <+> "logic" <+> brackets (int (typeSize elTy - 1) <> colon <> int 0) <+>
-              tyName ty <+> brackets (int 0 <> colon <> int (2^n-1)) <> semi
-    _ -> do case splitVecTy ty of
-              Just (ns,elTy') -> do
-                let ranges = hcat (mapM (\n' -> brackets (int 0 <> colon <> int (n'-1))) (tail ns))
-                "typedef" <+> elTy' <+> ranges <+> tyName ty <+> brackets (int 0 <> colon <> int (head ns - 1)) <> semi
-              _ -> error $ $(curLoc) ++ "impossible"
+    Vivado -> case splitVecTy ty of
+      Just ([Right n',Left n''],elTy') -> -- n' == 2^n
+        "typedef" <+> elTy' <+> brackets (int 0 <> colon <> int (n''-1)) <+>
+        tyName ty <+> brackets (int 0 <> colon <> int (n'-1)) <> semi
+      _ ->
+        "typedef" <+> "logic" <+> brackets (int (typeSize elTy - 1) <> colon <> int 0) <+>
+        tyName ty <+> brackets (int 0 <> colon <> int (2^n-1)) <> semi
+    _ -> case splitVecTy ty of
+      Just (Right n':ns,elTy') -> -- n' == 2^n
+        "typedef" <+> elTy' <+> hcat (mapM range ns) <+> tyName ty <+>
+        brackets (int 0 <> colon <> int (n' - 1)) <> semi
+      _ -> error $ $(curLoc) ++ "impossible"
 tyDec ty@(Product _ tys) | typeSize ty > 0 = Just A.<$> prodDec
   where
     prodDec = "typedef struct packed {" <$>
@@ -265,7 +279,7 @@ tyDec ty@(Product _ tys) | typeSize ty > 0 = Just A.<$> prodDec
 
 tyDec _ = pure Nothing
 
-splitVecTy :: HWType -> Maybe ([Int],SystemVerilogM Doc)
+splitVecTy :: HWType -> Maybe ([Either Int Int],SystemVerilogM Doc)
 splitVecTy = fmap splitElemTy . go
   where
     splitElemTy (ns,t) = case t of
@@ -274,16 +288,16 @@ splitVecTy = fmap splitElemTy . go
       Clock _ _   -> (ns, "logic")
       Reset _ _   -> (ns, "logic")
       String      -> (ns, "string")
-      Signed n    -> (ns ++ [n],"logic signed")
-      _           -> (ns ++ [typeSize t], "logic")
+      Signed n    -> (ns ++ [Left n],"logic signed")
+      _           -> (ns ++ [Left (typeSize t)], "logic")
 
     go (Vector n elTy) = case go elTy of
-      Just (ns,elTy') -> Just (n:ns,elTy')
-      _               -> Just ([n],elTy)
+      Just (ns,elTy') -> Just (Right n:ns,elTy')
+      _               -> Just ([Right n],elTy)
 
     go (RTree n elTy) = let n' = 2^n in case go elTy of
-      Just (ns,elTy') -> Just (n':ns,elTy')
-      _               -> Just ([n'],elTy)
+      Just (ns,elTy') -> Just (Right n':ns,elTy')
+      _               -> Just ([Right n'],elTy)
 
     go _ = Nothing
 
@@ -293,18 +307,14 @@ lvType ty@(Vector n elTy) | typeSize ty > 0 = Just A.<$> do
   case syn of
     Vivado -> "logic" <+> brackets (int 0 <> colon <> int (n-1)) <> brackets (int (typeSize elTy - 1) <> colon <> int 0)
     _ -> case splitVecTy ty of
-      Just (ns,elTy') -> do
-        let ranges = hcat (mapM (\n' -> brackets (int 0 <> colon <> int (n'-1))) ns)
-        elTy' <> ranges
+      Just (ns,elTy') -> elTy' <> hcat (mapM range ns)
       _ -> error $ $(curLoc) ++ "impossible"
 lvType ty@(RTree n elTy) | typeSize elTy > 0 = Just A.<$> do
   syn <- hdlSyn
   case syn of
     Vivado -> "logic" <+> brackets (int 0 <> colon <> int (2^n-1)) <> brackets (int (typeSize elTy - 1) <> colon <> int 0)
     _ -> case splitVecTy ty of
-      Just (ns,elTy') -> do
-        let ranges = hcat (mapM (\n' -> brackets (int 0 <> colon <> int (n'-1))) ns)
-        elTy' <> ranges
+      Just (ns,elTy') -> elTy' <> hcat (mapM range ns)
       _ -> error $ $(curLoc) ++ "impossible"
 lvType ty | typeSize ty > 0 = Just A.<$> verilogType ty
 lvType _ = pure Nothing
@@ -341,13 +351,18 @@ funDec ty@(Vector n elTy) | typeSize ty > 0 = Just A.<$>
     vecSigDecl d = do
       syn <- hdlSyn
       case syn of
-        Vivado -> "logic" <+> brackets (int (typeSize elTy - 1) <> colon <> int 0) <+>
-                  d <+> brackets (int 0 <> colon <> int (n-2))
-        _ -> do case splitVecTy ty of
-                  Just (ns,elTy') -> do
-                    let ranges' = hcat (mapM (\n' -> brackets (int 0 <> colon <> int (n'-1))) (tail ns))
-                    elTy' <+> ranges' <+> d <+> brackets (int 0 <> colon <> int (head ns - 2))
-                  _ -> error $ $(curLoc) ++ "impossible"
+        Vivado -> case splitVecTy ty of
+          Just ([Right n',Left n''],elTy') ->
+            elTy' <+> brackets (int 0 <> colon <> int (n''-1)) <+>
+            d <+> brackets (int 0 <> colon <> int (n'-2))
+          _ ->
+            "logic" <+> brackets (int (typeSize elTy - 1) <> colon <> int 0) <+>
+            d <+> brackets (int 0 <> colon <> int (n-2))
+        _ -> case splitVecTy ty of
+         Just (Right n':ns,elTy') ->
+           elTy' <+> hcat (mapM range ns) <+> d <+>
+           brackets (int 0 <> colon <> int (n' - 2))
+         _ -> error $ $(curLoc) ++ "impossible"
 
 
 funDec ty@(RTree n elTy) | typeSize elTy > 0 = Just A.<$>
@@ -375,13 +390,18 @@ funDec ty@(RTree n elTy) | typeSize elTy > 0 = Just A.<$>
     treeSigDecl d = do
       syn <- hdlSyn
       case syn of
-        Vivado -> "logic" <+> brackets (int (typeSize elTy - 1) <> colon <> int 0) <+>
-                  d <+> brackets (int 0 <> colon <> int (2^(n-1)-1))
-        _ -> do case splitVecTy (RTree (n-1) elTy) of
-                  Just (ns,elTy') -> do
-                    let ranges' = hcat (mapM (\n' -> brackets (int 0 <> colon <> int (n'-1))) (tail ns))
-                    elTy' <+> ranges' <+> d <+> brackets (int 0 <> colon <> int (head ns - 1))
-                  _ -> error $ $(curLoc) ++ "impossible"
+        Vivado -> case splitVecTy (RTree (n-1) elTy) of
+          Just ([Right n',Left n''],elTy') -> -- n' == 2 ^ (n-1)
+            elTy' <+> brackets (int 0 <> colon <> int (n''-1)) <+>
+            d <+> brackets (int 0 <> colon <> int (n' - 1))
+          _ ->
+            "logic" <+> brackets (int (typeSize elTy - 1) <> colon <> int 0) <+>
+            d <+> brackets (int 0 <> colon <> int (2^(n-1)-1))
+        _ -> case splitVecTy (RTree (n-1) elTy) of
+          Just (Right n':ns,elTy') -> -- n' == 2 ^ (n-1)
+            elTy' <+> hcat (mapM range ns) <+> d <+>
+            brackets (int 0 <> colon <> int (n' - 1))
+          _ -> error $ $(curLoc) ++ "impossible"
 
     tName  = tyName ty
     ranges = brackets (int 0 <> colon <> int (2^n-1)) <>
@@ -514,12 +534,12 @@ verilogTypeErrValue :: HWType -> SystemVerilogM Doc
 verilogTypeErrValue (Vector n elTy) = do
   syn <- hdlSyn
   case syn of
-    Vivado -> braces (int n <+> braces (int (typeSize elTy) <+> braces "1'bx"))
+    Vivado -> char '\'' <> braces (int n <+> braces (braces (int (typeSize elTy) <+> braces "1'bx")))
     _ -> char '\'' <> braces (int n <+> braces (verilogTypeErrValue elTy))
 verilogTypeErrValue (RTree n elTy) = do
   syn <- hdlSyn
   case syn of
-    Vivado -> braces (int (2^n) <+> braces (int (typeSize elTy) <+> braces "1'bx"))
+    Vivado -> char '\'' <> braces (int (2^n) <+> braces (braces (int (typeSize elTy) <+> braces "1'bx")))
     _ -> char '\'' <> braces (int (2^n) <+> braces (verilogTypeErrValue elTy))
 verilogTypeErrValue String = "\"ERROR\""
 verilogTypeErrValue ty  = braces (int (typeSize ty) <+> braces "1'bx")

clash-verilog/CHANGELOG.md

@@ -1,5 +1,9 @@
 # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package
 
+##
+* Fixes bugs:
+  * Incorrect unsigned->signed wrap-around and conversion
+
 ## 0.7 *January 16th 2017*
 * New features:
   * Support `clash-prelude` 0.11

clash-vhdl/CHANGELOG.md

@@ -1,5 +1,9 @@
 # Changelog for the [`clash-vhdl`](http://hackage.haskell.org/package/clash-vhdl) package
 
+##
+* Fixes bugs:
+  * resize `Integer` multiplication result
+
 ## 0.7 *January 16th 2017*
 * New features:
   * Support `clash-prelude` 0.11

clash-vhdl/primitives/CLaSH.Sized.RTree.json

@@ -12,8 +12,9 @@
 textract_~SYM[0] : block
   signal ~SYM[1] : ~TYP[0];
 begin
-  ~SYM[1] <= ~ARG[0];
-  ~RESULT <= ~SYM[1](0);
+  ~SYM[1] <= ~ARG[0];~IF ~VIVADO ~THEN
+  ~RESULT <= ~FROMBV[~SYM[1](0)][~TYPO];~ELSE
+  ~RESULT <= ~SYM[1](0);~FI
 end block;
 -- textract end"
     }

clash-vhdl/src/CLaSH/Backend/VHDL.hs

@@ -649,7 +649,13 @@ expr_ _ (Identifier id_ (Just (Indexed ((Vector _ elTy),1,1)))) = do
     _ -> text id_ <> parens (int 0)
 expr_ _ (Identifier id_ (Just (Indexed ((Vector n _),1,2)))) = text id_ <> parens (int 1 <+> "to" <+> int (n-1))
 
-expr_ _ (Identifier id_ (Just (Indexed ((RTree 0 _),0,1)))) = text id_ <> parens (int 0)
+expr_ _ (Identifier id_ (Just (Indexed ((RTree 0 elTy),0,1)))) = do
+  syn <- hdlSyn
+  case syn of
+    Vivado -> do
+      id' <- fmap (displayT . renderOneLine) (text id_ <> parens (int 0))
+      fromSLV elTy id' (typeSize elTy - 1) 0
+    _ -> text id_ <> parens (int 0)
 expr_ _ (Identifier id_ (Just (Indexed ((RTree n _),1,1)))) =
   let z = 2^(n-1)
   in  text id_ <> parens (int 0 <+> "to" <+> int (z-1))
@@ -672,7 +678,13 @@ expr_ _ (Identifier id_ (Just (Indexed ((Vector _ elTy),10,fI)))) = do
 -- This is a HACK for CLaSH.Driver.TopWrapper.mkOutput
 -- RTree's don't have a 10'th constructor, this is just so that we can
 -- recognize the particular case
-expr_ _ (Identifier id_ (Just (Indexed ((RTree _ _),10,fI)))) = text id_ <> parens (int fI)
+expr_ _ (Identifier id_ (Just (Indexed ((RTree _ elTy),10,fI)))) = do
+  syn <- hdlSyn
+  case syn of
+    Vivado -> do
+      id' <- fmap (displayT . renderOneLine) (text id_ <> parens (int fI))
+      fromSLV elTy id' (typeSize elTy - 1) 0
+    _ -> text id_ <> parens (int fI)
 
 expr_ _ (Identifier id_ (Just (DC (ty@(SP _ _),_)))) = text id_ <> parens (int start <+> "downto" <+> int end)
   where
@@ -712,17 +724,10 @@ expr_ _ (DataCon ty@(RTree 0 elTy) _ [e]) = do
   case syn of
     Vivado -> vhdlTypeMark ty <> "'" <> parens (int 0 <+> rarrow <+> toSLV elTy e)
     _ -> vhdlTypeMark ty <> "'" <> parens (int 0 <+> rarrow <+> expr_ False e)
-expr_ _ e@(DataCon ty@(RTree d elTy) _ [e1,e2]) = do
-  syn <- hdlSyn
-  case syn of
-    Vivado -> vhdlTypeMark ty <> "'" <> case rtreeChain e of
-      Just es -> tupled (mapM (toSLV elTy) es)
-      Nothing -> parens ("std_logic_vector'" <> parens (toSLV elTy e1) <+>
-                         "&" <+> expr_ False e2)
-    _ -> vhdlTypeMark ty <> "'" <> case rtreeChain e of
-      Just es -> tupled (mapM (expr_ False) es)
-      Nothing -> parens (vhdlTypeMark (RTree (d-1) elTy) <> "'" <> parens (expr_ False e1) <+>
-                         "&" <+> expr_ False e2)
+expr_ _ e@(DataCon ty@(RTree d elTy) _ [e1,e2]) = vhdlTypeMark ty <> "'" <> case rtreeChain e of
+  Just es -> tupled (mapM (expr_ False) es)
+  Nothing -> parens (vhdlTypeMark (RTree (d-1) elTy) <> "'" <> parens (expr_ False e1) <+>
+                     "&" <+> expr_ False e2)
 
 expr_ _ (DataCon ty@(SP _ args) (DC (_,i)) es) = assignExpr
   where