Release v3.0a
·
116 commits
to master
since this release
- Added
- Support for separate RISC-V Bios and Kernel
- Command line option
flush-sim-memto flush simulator memory hierarchy on every fresh simulation run - Command line option
sim-traceto generate instruction commit trace during simulation - Distinct configurable read-hit and write-hit latency for all the caches
- Return address stack (RAS)
- Branch prediction and speculative execution support for out of order core
- Print performance counters on terminal when the simulation completes
- More performance counters:
- Instruction types
- ecall
- page walks for loads, stores and instructions
- memory controller delay for data and instructions
- hardware interrupts
- Changed
- Port to TinyEMU version
2019-12-21 - For bimodal branch predictor, store prediction bits in a separate Branch history table (BHT)
- For in-order core, non-memory instructions can forward their result from MEM stage in addition to EX stage
- For in-order core, relaxed interlocking on WAW data hazard
- Simplified out of order core design, ROB slots are now used as physical registers along with a single rename table and a single global issue queue
- Port to TinyEMU version
- Fixed
- Correctly calculated the rounding mode for floating pointing instruction decoding
- Converted
c.addiwresult buffer intoint32_ton 64-bit simulation - Set the data type to
unint64_tfor 64-bit simulation, for the buffer which holds the memory address for atomic instructions - Issue #13 and #14 (thanks to Okhotnikov Grigory)