Skip to content

Commit

Permalink
README.md: fix url for simulate script
Browse files Browse the repository at this point in the history
  • Loading branch information
gkothar1 authored Jun 6, 2020
1 parent a24cb36 commit 17283c1
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions README.md
Original file line number Diff line number Diff line change
Expand Up @@ -136,7 +136,7 @@ int main()
```

### Using the simulate script
Alternatively, users can use the simulation script (`simulate.c`) provided [here](https://github.com/bucaps/marss-riscv/tree/master/scripts), which forks a child process. The child enters the simulation mode and execs the command. The parent process waits for the child to complete and then switches MARSS-RISCV back to emulation mode. With this script, it is possible to simulate any program without the need to modify and recompile the source code. Since the child switches to simulation mode before calling `exec()`, `exec()` also runs in the simulation. Hence, performance statistics generated at the end of the simulation will also include stats for `exec()`.
Alternatively, users can use the simulation script (`simulate.c`) provided [here](https://github.com/bucaps/marss-riscv-utils/blob/master/simulate.c), which forks a child process. The child enters the simulation mode and execs the command. The parent process waits for the child to complete and then switches MARSS-RISCV back to emulation mode. With this script, it is possible to simulate any program without the need to modify and recompile the source code. Since the child switches to simulation mode before calling `exec()`, `exec()` also runs in the simulation. Hence, performance statistics generated at the end of the simulation will also include stats for `exec()`.

### Running benchmarks
We have provided a detailed step-by-step comprehensive tutorial [here](https://marss-riscv-docs.readthedocs.io/en/latest/sections/running-full-system.html) to run the benchmarks on the simulator. This tutorial configures MARSS-RISCV to simulate a simple 5-stage 32-bit in-order RISC-V processor and run [CoreMark](https://github.com/eembc/coremark), an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcontrollers (MCU).
Expand Down Expand Up @@ -205,4 +205,4 @@ TinyEMU:
## License
* This project is licensed under the MIT License - refer to the [LICENSE.md](LICENSE.md) file for details.
* The SLIRP library has a two clause BSD license.
* DRAMSim2 has a two clause BSD license.
* DRAMSim2 has a two clause BSD license.

0 comments on commit 17283c1

Please sign in to comment.