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@barthess
barthess committed Dec 11, 2015
1 parent 022ea7e commit ba54e40
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Showing 8 changed files with 354 additions and 36 deletions.
18 changes: 11 additions & 7 deletions fsmc2bram.xise
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Expand Up @@ -19,13 +19,6 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="mnu.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="rtl/fsmc2bram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="rtl/ram_addr_test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="129"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
Expand All @@ -38,6 +31,17 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="rtl/fsmc2bram_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="rtl/fsmc2bram_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="mnu_async.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/bram.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
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2 changes: 1 addition & 1 deletion ipcore_dir/bram.xco
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@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Fri Nov 20 14:11:34 2015
# Date: Tue Nov 24 08:35:39 2015
#
##############################################################
#
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22 changes: 11 additions & 11 deletions ipcore_dir/clk_src.xco
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@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Tue Nov 10 07:24:04 2015
# Date: Tue Nov 24 10:37:51 2015
#
##############################################################
#
Expand Down Expand Up @@ -70,16 +70,16 @@ CSET clkin2_jitter_ps=100.0
CSET clkin2_ui_jitter=0.010
CSET clkout1_drives=BUFG
CSET clkout1_requested_duty_cycle=50.000
CSET clkout1_requested_out_freq=90.000
CSET clkout1_requested_out_freq=180.000
CSET clkout1_requested_phase=0.000
CSET clkout2_drives=BUFG
CSET clkout2_requested_duty_cycle=50.000
CSET clkout2_requested_out_freq=180.000
CSET clkout2_requested_out_freq=150.000
CSET clkout2_requested_phase=0.000
CSET clkout2_used=true
CSET clkout3_drives=BUFG
CSET clkout3_requested_duty_cycle=50.000
CSET clkout3_requested_out_freq=360.000
CSET clkout3_requested_out_freq=130.000
CSET clkout3_requested_phase=0.000
CSET clkout3_used=true
CSET clkout4_drives=BUFG
Expand Down Expand Up @@ -107,15 +107,15 @@ CSET component_name=clk_src
CSET daddr_port=DADDR
CSET dclk_port=DCLK
CSET dcm_clk_feedback=1X
CSET dcm_clk_out1_port=CLK0
CSET dcm_clk_out1_port=CLKFX
CSET dcm_clk_out2_port=CLK0
CSET dcm_clk_out3_port=CLK0
CSET dcm_clk_out4_port=CLK0
CSET dcm_clk_out5_port=CLK0
CSET dcm_clk_out6_port=CLKFX
CSET dcm_clkdv_divide=2.0
CSET dcm_clkfx_divide=3
CSET dcm_clkfx_multiply=4
CSET dcm_clkfx_divide=27
CSET dcm_clkfx_multiply=25
CSET dcm_clkgen_clk_out1_port=CLKFX
CSET dcm_clkgen_clk_out2_port=CLKFX
CSET dcm_clkgen_clk_out3_port=CLKFX
Expand Down Expand Up @@ -197,16 +197,16 @@ CSET override_pll=false
CSET platform=lin64
CSET pll_bandwidth=OPTIMIZED
CSET pll_clk_feedback=CLKFBOUT
CSET pll_clkfbout_mult=40
CSET pll_clkfbout_mult=33
CSET pll_clkfbout_phase=0.000
CSET pll_clkin_period=37.037
CSET pll_clkout0_divide=12
CSET pll_clkout0_divide=5
CSET pll_clkout0_duty_cycle=0.500
CSET pll_clkout0_phase=0.000
CSET pll_clkout1_divide=6
CSET pll_clkout1_duty_cycle=0.500
CSET pll_clkout1_phase=0.000
CSET pll_clkout2_divide=3
CSET pll_clkout2_divide=7
CSET pll_clkout2_duty_cycle=0.500
CSET pll_clkout2_phase=0.000
CSET pll_clkout3_divide=10
Expand Down Expand Up @@ -266,4 +266,4 @@ CSET use_status=false
MISC pkg_timestamp=2012-05-10T12:44:55Z
# END Extra information
GENERATE
# CRC: 6ef5a02
# CRC: 632adfbf
153 changes: 153 additions & 0 deletions mnu_async.ucf
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@@ -0,0 +1,153 @@
# main clock constrains
NET "CLK_IN_27MHZ" IOSTANDARD = LVCMOS33;
NET "CLK_IN_27MHZ" LOC = AB10;
NET "CLK_IN_27MHZ" TNM_NET = "CLK_IN_27MHZ";
TIMESPEC "TS_CLK_IN_27MHZ" = PERIOD "CLK_IN_27MHZ" 37.037 ns HIGH 50% INPUT_JITTER 74.074ps;

NET "DEV_NULL_BANK1" LOC = R17;
NET "DEV_NULL_BANK1" IOSTANDARD = LVCMOS33;
NET "DEV_NULL_BANK1" DRIVE = 2;
NET "DEV_NULL_BANK1" SLEW = SLOW;

NET "DEV_NULL_BANK0" LOC = B18;
NET "DEV_NULL_BANK0" IOSTANDARD = LVCMOS33;
NET "DEV_NULL_BANK0" DRIVE = 2;
NET "DEV_NULL_BANK0" SLEW = SLOW;

NET "STM_IO_FPGA_READY" LOC = J16; # IO_3
NET "STM_IO_FPGA_READY" IOSTANDARD = LVCMOS33;
NET "STM_IO_MUL_RDY" LOC = A20; # IO_5
NET "STM_IO_MUL_RDY" IOSTANDARD = LVCMOS33; # IO_5
NET "STM_IO_MUL_DV" LOC = A21; # IO_6
NET "STM_IO_MUL_DV" IOSTANDARD = LVCMOS33; # IO_6
NET "STM_IO_MMU_INT" LOC = H17; # IO_7
NET "STM_IO_MMU_INT" IOSTANDARD = LVCMOS33; # IO_7
NET "STM_IO_OLD_FSMC_CLK" LOC = K17; # IO_4 - old FSMC clock, hardwired to TIM8_CH2
NET "STM_IO_OLD_FSMC_CLK" IOSTANDARD = LVCMOS33; # IO_4

NET "FSMC_NOE" LOC = V18;
NET "FSMC_NWE" LOC = V17;
NET "FSMC_NCE" LOC = V20;
NET "FSMC_NCE" IOSTANDARD = LVCMOS33;
NET "FSMC_NOE" IOSTANDARD = LVCMOS33;
NET "FSMC_NWE" IOSTANDARD = LVCMOS33;

NET "FSMC_NBL[1]" LOC = T17;
NET "FSMC_NBL[0]" LOC = T18;
NET "FSMC_NBL[0]" IOSTANDARD = LVCMOS33;
NET "FSMC_NBL[1]" IOSTANDARD = LVCMOS33;

NET "FSMC_A[22]" IOSTANDARD = LVCMOS33;
NET "FSMC_A[21]" IOSTANDARD = LVCMOS33;
NET "FSMC_A[20]" IOSTANDARD = LVCMOS33;
NET "FSMC_A[19]" IOSTANDARD = LVCMOS33;
NET "FSMC_A[18]" IOSTANDARD = LVCMOS33;
NET "FSMC_A[17]" IOSTANDARD = LVCMOS33;
NET "FSMC_A[16]" IOSTANDARD = LVCMOS33;
NET "FSMC_A[15]" IOSTANDARD = LVCMOS33;
NET "FSMC_A[14]" IOSTANDARD = LVCMOS33;
NET "FSMC_A[13]" IOSTANDARD = LVCMOS33;
NET "FSMC_A[12]" IOSTANDARD = LVCMOS33;
NET "FSMC_A[11]" IOSTANDARD = LVCMOS33;
NET "FSMC_A[10]" IOSTANDARD = LVCMOS33;
NET "FSMC_A[9]" IOSTANDARD = LVCMOS33;
NET "FSMC_A[8]" IOSTANDARD = LVCMOS33;
NET "FSMC_A[7]" IOSTANDARD = LVCMOS33;
NET "FSMC_A[6]" IOSTANDARD = LVCMOS33;
NET "FSMC_A[5]" IOSTANDARD = LVCMOS33;
NET "FSMC_A[4]" IOSTANDARD = LVCMOS33;
NET "FSMC_A[3]" IOSTANDARD = LVCMOS33;
NET "FSMC_A[2]" IOSTANDARD = LVCMOS33;
NET "FSMC_A[1]" IOSTANDARD = LVCMOS33;
NET "FSMC_A[0]" IOSTANDARD = LVCMOS33;
NET "FSMC_D[15]" IOSTANDARD = LVCMOS33;
NET "FSMC_D[14]" IOSTANDARD = LVCMOS33;
NET "FSMC_D[13]" IOSTANDARD = LVCMOS33;
NET "FSMC_D[12]" IOSTANDARD = LVCMOS33;
NET "FSMC_D[11]" IOSTANDARD = LVCMOS33;
NET "FSMC_D[10]" IOSTANDARD = LVCMOS33;
NET "FSMC_D[9]" IOSTANDARD = LVCMOS33;
NET "FSMC_D[8]" IOSTANDARD = LVCMOS33;
NET "FSMC_D[7]" IOSTANDARD = LVCMOS33;
NET "FSMC_D[6]" IOSTANDARD = LVCMOS33;
NET "FSMC_D[5]" IOSTANDARD = LVCMOS33;
NET "FSMC_D[4]" IOSTANDARD = LVCMOS33;
NET "FSMC_D[3]" IOSTANDARD = LVCMOS33;
NET "FSMC_D[2]" IOSTANDARD = LVCMOS33;
NET "FSMC_D[1]" IOSTANDARD = LVCMOS33;
NET "FSMC_D[0]" IOSTANDARD = LVCMOS33;


NET "FSMC_D[0]" LOC = R16;
NET "FSMC_D[1]" LOC = T15;
NET "FSMC_D[2]" LOC = Y20;
NET "FSMC_D[3]" LOC = Y19;
NET "FSMC_D[4]" LOC = P18;
NET "FSMC_D[5]" LOC = P17;
NET "FSMC_D[6]" LOC = AB20;
NET "FSMC_D[7]" LOC = AB19;
NET "FSMC_D[8]" LOC = P20;
NET "FSMC_D[9]" LOC = P19;
NET "FSMC_D[10]" LOC = Y22;
NET "FSMC_D[11]" LOC = Y21;
NET "FSMC_D[12]" LOC = P16;
NET "FSMC_D[13]" LOC = P15;
NET "FSMC_D[14]" LOC = AB21;
NET "FSMC_D[15]" LOC = AA20;
NET "FSMC_A[0]" LOC = T13;
NET "FSMC_A[1]" LOC = T12;
NET "FSMC_A[2]" LOC = W22;
NET "FSMC_A[3]" LOC = W20;
NET "FSMC_A[4]" LOC = R13;
NET "FSMC_A[5]" LOC = R12;
NET "FSMC_A[6]" LOC = AA22;
NET "FSMC_A[7]" LOC = AA21;
NET "FSMC_A[8]" LOC = V22;
NET "FSMC_A[9]" LOC = V21;
NET "FSMC_A[10]" LOC = U22;
NET "FSMC_A[11]" LOC = U20;
NET "FSMC_A[12]" LOC = T22;
NET "FSMC_A[13]" LOC = T21;
NET "FSMC_A[14]" LOC = R22;
NET "FSMC_A[15]" LOC = R20;
NET "FSMC_A[16]" LOC = P22;
NET "FSMC_A[17]" LOC = P21;
NET "FSMC_A[18]" LOC = N22;
NET "FSMC_A[19]" LOC = N20;
NET "FSMC_A[20]" LOC = M20;
NET "FSMC_A[21]" LOC = N19;
NET "FSMC_A[22]" LOC = M22;

NET "FSMC_D[15]" DRIVE = 4;
NET "FSMC_D[14]" DRIVE = 4;
NET "FSMC_D[13]" DRIVE = 4;
NET "FSMC_D[12]" DRIVE = 4;
NET "FSMC_D[11]" DRIVE = 4;
NET "FSMC_D[10]" DRIVE = 4;
NET "FSMC_D[9]" DRIVE = 4;
NET "FSMC_D[8]" DRIVE = 4;
NET "FSMC_D[7]" DRIVE = 4;
NET "FSMC_D[6]" DRIVE = 4;
NET "FSMC_D[5]" DRIVE = 4;
NET "FSMC_D[4]" DRIVE = 4;
NET "FSMC_D[3]" DRIVE = 4;
NET "FSMC_D[2]" DRIVE = 4;
NET "FSMC_D[1]" DRIVE = 4;
NET "FSMC_D[0]" DRIVE = 4;
NET "FSMC_D[15]" SLEW = FAST;
NET "FSMC_D[14]" SLEW = FAST;
NET "FSMC_D[13]" SLEW = FAST;
NET "FSMC_D[12]" SLEW = FAST;
NET "FSMC_D[11]" SLEW = FAST;
NET "FSMC_D[10]" SLEW = FAST;
NET "FSMC_D[9]" SLEW = FAST;
NET "FSMC_D[8]" SLEW = FAST;
NET "FSMC_D[7]" SLEW = FAST;
NET "FSMC_D[6]" SLEW = FAST;
NET "FSMC_D[5]" SLEW = FAST;
NET "FSMC_D[4]" SLEW = FAST;
NET "FSMC_D[3]" SLEW = FAST;
NET "FSMC_D[2]" SLEW = FAST;
NET "FSMC_D[1]" SLEW = FAST;
NET "FSMC_D[0]" SLEW = FAST;

0 mnu.ucf → mnu_sync.ucf
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