nop

barthess · Dec 22, 2015 · a3d5d73 · a3d5d73
1 parent ada79ac
commit a3d5d73
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Showing 3 changed files with 8 additions and 8 deletions.
diff --git a/fsmc2bram.xise b/fsmc2bram.xise
@@ -19,10 +19,6 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
     </file>
-    <file xil_pn:name="rtl/ram_addr_test.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="129"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
-    </file>
     <file xil_pn:name="ipcore_dir/bram.xco" xil_pn:type="FILE_COREGEN">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
@@ -42,6 +38,10 @@
     <file xil_pn:name="mnu_async.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
+    <file xil_pn:name="rtl/memtest_assist.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
     <file xil_pn:name="ipcore_dir/bram.xise" xil_pn:type="FILE_COREGENISE">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>

diff --git a/rtl/ram_addr_test.vhd → rtl/memtest_assist.vhd b/rtl/ram_addr_test.vhd → rtl/memtest_assist.vhd
@@ -4,7 +4,7 @@ use ieee.std_logic_unsigned.all;
 use ieee.numeric_std.all;
 
 
-entity ram_addr_test is
+entity memtest_assist is
   generic (
     AW : positive
   );
@@ -21,10 +21,10 @@ entity ram_addr_test is
 		BRAM_EN     : out std_logic;   -- memory enable
 		BRAM_WE     : out std_logic_vector(0    downto 0)    -- memory write enable
   );
-end entity ram_addr_test;
+end entity memtest_assist;
 
 
-architecture rtl of ram_addr_test is
+architecture rtl of memtest_assist is
   signal addr_cnt : std_logic_vector (AW-1 downto 0);
 begin
 	BRAM_CLK <= clk_i;

diff --git a/rtl/root.vhd b/rtl/root.vhd
@@ -102,7 +102,7 @@ begin
 	);
 
 
-  ram_addr_test : entity work.ram_addr_test
+  memtest_assist : entity work.memtest_assist
   generic map (
     AW => FSMC_A_USED
   )