Update revisions

Cores-VeeR-EL2 9163d5f7fb8 Merge pull request #302 from chipsalliance/waive-ifu-write-channel
7c64bc9bb84 el2_veer: waive IFU AXI write channel
a0a2e224f03 Merge pull request #294 from chipsalliance/custom-riscv-dv-runs
b6a0c77062c ahb_lsu_dma_bridge: use TAG param in the bridge instance
0c75594cf22 Makefile: add ahb_lsu_dma_bridge.sv to TBFILES
d2194dce28d verif: pmp: format
928a07bc0d3 verif: pmp: update test to work with python3.9
16b98c7771f verif: pmp: reset core at start
51504e298e9 verif: pmp: flatten cfg_pkt in wrapper
0f529cfc55f testbench: add test programs hexes
dc941742622 CI: add Custom regression exceptions tests step
86e329585c6 verification: ahb_sif: Use legal index value
fffc16c972f CI: add custom uarch tests step
b5baa0cd24f verif: dma: do not set cmd_type in reset
bb9a2f0c0ee verif: dccm: fix multidriven
633b7e512c6 verif: iccm: remove multidrivers, initialize signals on reset
4e78cddce7b verif: dmi: fix space define and wait for reset before looping
177edfc313b verif: ahb_2_axi: initialize inputs
d133540be34 verif: axi_to_ahb: wait for reset before looping
9439036bdd6 verif: axi_to_ahb: initialize inputs
f5396b84202 verif: dma: set clk_en=1
5e3fb25dadd verif: dma: tie inputs to gnd on reset
88a1bdc1df2 verif: pic: tie inputs to gnd on reset
93abf5ae4a9 verif: exu_div: tie input to gnd on reset
fe2193434eb verif:exu_mul: tie inputs to gnd on reset
b038714175b run custom coverage in PRs
95ea2d313d0 testbench: ahb_sif: initialize bvalid
b791c129c1e tb: tie dangling signals in non-Verilator sim
150334e9335 Merge pull request #298 from chipsalliance/merge-coverage-data
f32596230c8 Merge pull request #299 from chipsalliance/improve-cov-deps-versioning
5db2d3c191f Merge pull request #301 from chipsalliance/optimize-page-deployment
6c8708db7b2 CI: publish-webpage: pack webpage before uploading it as artifact
9d6bf35f058 CI: publish-webpage: move data instead of copying it
b8a4e7d14ea CI: upload combined coverage data
709ae558077 Version coverage dependencies in a single place

deps.json

@@ -1 +1 @@
-{"cores": [{"repository_name": "ibex", "repository_url": "https://github.com/lowRISC/ibex", "repository_branch": "master", "repository_revision": "8f4c75c5e43e61b994248307c814e01860303056"}, {"repository_name": "Cores-VeeR-EL2", "repository_url": "https://github.com/chipsalliance/Cores-VeeR-EL2", "repository_branch": "main", "repository_revision": "1637d9751b03baa6615b8c97a2612fce2c3a9ea0"}, {"repository_name": "caliptra-rtl", "repository_url": "https://github.com/chipsalliance/caliptra-rtl", "repository_branch": "main", "repository_revision": "de9d9c8685485bc5152ac81bd6ad42d6e167afe4"}]}
+{"cores": [{"repository_name": "ibex", "repository_url": "https://github.com/lowRISC/ibex", "repository_branch": "master", "repository_revision": "8f4c75c5e43e61b994248307c814e01860303056"}, {"repository_name": "Cores-VeeR-EL2", "repository_url": "https://github.com/chipsalliance/Cores-VeeR-EL2", "repository_branch": "main", "repository_revision": "9163d5f7fb84ad464a0b31ee6bced5008b3638a8"}, {"repository_name": "caliptra-rtl", "repository_url": "https://github.com/chipsalliance/caliptra-rtl", "repository_branch": "main", "repository_revision": "de9d9c8685485bc5152ac81bd6ad42d6e167afe4"}]}