Add rule for generating filelist out of Verilog library

Internal-tag: [#70063]
Signed-off-by: Maciej Kurc <[email protected]>

verilog/defs.bzl

@@ -1,5 +1,9 @@
 """verilog rules"""
 
+load(
+    ":filelist.bzl",
+    _verilog_filelist = "verilog_filelist",
+)
 load(
     ":providers.bzl",
     _VerilogInfo = "VerilogInfo",
@@ -8,3 +12,4 @@ load(
 
 VerilogInfo = _VerilogInfo
 verilog_library = _verilog_library
+verilog_filelist = _verilog_filelist

verilog/filelist.bzl

@@ -0,0 +1,54 @@
+"""Verilog filelist generation rules"""
+
+load(":providers.bzl", "VerilogInfo")
+
+def _verilog_filelist_impl(ctx):
+    """Collects all direct and transitive sources/headers of a verilog library"""
+
+    # Sources
+    srcs = depset([], transitive = [ctx.attr.lib[VerilogInfo].dag]).to_list()
+
+    # Flatten
+    all_srcs = [info.srcs for info in srcs]
+    all_hdrs = [info.hdrs for info in srcs]
+
+    all_srcs = [f for sub_tuple in all_srcs for f in sub_tuple]
+    all_hdrs = [f for sub_tuple in all_hdrs for f in sub_tuple]
+
+    # Include directories
+    include_dirs = depset([f.dirname for f in all_hdrs]).to_list()
+
+    # Write the .f file
+    content = []
+
+    for name in include_dirs:
+        content.append(ctx.attr.include_prefix + name)
+
+    for name in all_srcs:
+        content.append(name.path)
+
+    file = ctx.actions.declare_file(ctx.label.name + ".f")
+    ctx.actions.write(file, "\n".join(content) + "\n")
+
+    return DefaultInfo(
+        files = depset([file]),
+    )
+
+verilog_filelist = rule(
+    doc = "Generate a .f file from a Verilog library.",
+    implementation = _verilog_filelist_impl,
+    attrs = {
+        "include_prefix": attr.string(
+            doc = "Prefix for include directories",
+            default = "+incdir+",
+        ),
+        "lib": attr.label(
+            doc = "The Verilog library to use",
+            providers = [VerilogInfo],
+            mandatory = True,
+        ),
+    },
+    provides = [
+        DefaultInfo,
+    ],
+)

verilog/tests/BUILD

@@ -0,0 +1,41 @@
+load("//verilog:defs.bzl", "verilog_filelist", "verilog_library")
+
+package(
+    default_applicable_licenses = ["//:package_license"],
+    default_visibility = ["//visibility:private"],
+)
+
+verilog_library(
+    name = "not",
+    srcs = [
+        "not.v",
+    ],
+)
+
+verilog_library(
+    name = "top",
+    srcs = [
+        "top.v",
+    ],
+    hdrs = [
+        "defs.vh",
+    ],
+    deps = [
+        ":not",
+    ],
+)
+
+verilog_filelist(
+    name = "top_filelist",
+    lib = ":top",
+)
+
+genrule(
+    name = "top_filelist_test",
+    srcs = [
+        "golden.f",
+        ":top_filelist",
+    ],
+    outs = ["diff.txt"],
+    cmd = "diff $(SRCS) > $(OUTS)",
+)

verilog/tests/defs.vh

@@ -0,0 +1 @@
+`define COUNT 5

verilog/tests/golden.f

@@ -0,0 +1,3 @@
++incdir+verilog/tests
+verilog/tests/not.v
+verilog/tests/top.v

verilog/tests/not.v

@@ -0,0 +1,8 @@
+module not_gate(
+    input  wire A,
+    output wire Y
+);
+
+    assign Y = !A;
+
+endmodule

verilog/tests/top.v

@@ -0,0 +1,21 @@
+`include "defs.vh"
+
+module top(
+    input  wire A,
+    output wire Y
+);
+
+    wire [`COUNT:0] y;
+
+    genvar i;
+    generate for (i = 0; i < `COUNT; i = i + 1) begin
+        not_gate xnot_gate (
+            .A (y[i]),
+            .Y (y[i+1])
+        );
+    end endgenerate
+
+    assign y[0] = A;
+    assign Y    = y[`COUNT];
+
+endmodule